Fetching data between thread execution in a flash/DRAM/embedded DRAM-equipped system

• US 9,189,442 B1
• Filed: 01/05/2015
• Issued: 11/17/2015
• Est. Priority Date: 04/06/2011
• Status: Active Grant

• Current Assignee: P4tents1 LLC
• Original Assignee: P4tents1 LLC
• Inventors: Smith, Michael S
• Primary Examiner(s): Cardwell, Eric S
• Application Number:
  US14/589,942
• Time in Patent Office: 316 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0824 Distributed directories, e.g. linked lists of caches
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 9/44557 Code layout in executable memory
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/4824 : Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus and associated method/processing unit are provided for utilizing a memory subsystem including NAND flash memory and dynamic random access memory. Further included is a first circuit for receiving DDR signals and converting the DDR signals to SATA signals. The first circuit includes embedded dynamic random access memory. Also provided is a second circuit for receiving the SATA signals and converting the SATA signals to NAND flash signals. The second circuit is communicatively coupled to the first circuit via a first memory bus associated with a SATA protocol, the NAND flash memory via a second memory bus associated with a NAND flash protocol, and the dynamic random access memory. In operation, data is fetched using a time between an execution of a plurality of threads.

Claims

1. An apparatus, comprising:

NAND flash memory;

random access memory;

additional memory;

a first circuit for receiving DDR signals and outputting SATA signals, the first circuit communicatively coupled to the additional memory, and further capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and

a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory;

said apparatus configured such that;

said first circuit;

receives a first command including first data via the first bus for causing at least a portion of a random access data read,

stores at least a portion of the first command in the additional memory,

generates, in response to the first command, a second command including second data that is based on at least a portion of the first data, and

sends the second command to the second circuit via the second bus;

said second circuit;

receives the second command from the first circuit via the second bus,

generates, in response to the second command, a third command including third data that is based on at least a portion of the second data, and

sends the third command to the NAND flash memory via the third bus for causing first information in the NAND flash memory to be written to the random access memory;

said first circuit;

receives a status query via the first bus for checking a status in connection with the first information, and

allows, in response to the status query, the status to be checked in connection with the first information;

said first circuit;

receives a fourth command including fourth data via the first bus for causing the first information to be read from the random access memory, and

sends, in response to the fourth command, the first information from the random access memory to a processor via the first bus.

2. The apparatus of claim 1, wherein said apparatus is configured such that said first circuit:

receives a fifth command including fifth data via the first bus for causing at least a portion of a random access data write,

stores at least a portion of the fifth command in the additional memory,

generates, in response to the fifth command, a sixth command including sixth data that is based on at least a portion of the fifth data, and

sends the sixth command to the second circuit via the second bus.

3. The apparatus of claim 2, wherein said apparatus is configured such that said second circuit:

receives the sixth command from the first circuit via the second bus,

generates, in response to the sixth command, a seventh command including seventh data that is based on at least a portion of the sixth data, and

sends the seventh command to the NAND flash memory via the third bus for causing second information to be written to the NAND flash memory.

4. The apparatus of claim 3, wherein said apparatus is configured such that said first circuit:

receives a second status query via the first bus for checking a status in connection with the second information, and

allows, in response to the second status query, the status to be checked in connection with the second information.

5. The apparatus of claim 2, wherein said apparatus is configured for performing the random access data write, at least in part, before receiving the fourth command.

6. The apparatus of claim 5, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes storing the at least portion of the fifth command in the additional memory.

7. The apparatus of claim 5, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes causing the second information to be written to the NAND flash memory.

8. The apparatus of claim 2, wherein said apparatus is configured such that the fifth command is received and the random access data write is performed at least in part, before the first information is sent.

9. The apparatus of claim 8, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes storing the at least portion of the fifth command in the additional memory.

10. The apparatus of claim 8, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes causing the second information to be written to the NAND flash memory.

11. The apparatus of claim 2, wherein said apparatus is configured for performing the random access data write, at least in part, before the status query is received.

12. The apparatus of claim 11, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes storing the at least portion of the fifth command in the additional memory.

13. The apparatus of claim 11, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes causing the second information to be written to the NAND flash memory.

14. The apparatus of claim 2, wherein said apparatus is configured for performing the random access data write, at least in part, before the first information in the NAND flash memory is caused to be written to the random access memory.

15. The apparatus of claim 14, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes storing the at least portion of the fifth command in the additional memory.

16. The apparatus of claim 14, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes causing the second information to be written to the NAND flash memory.

17. The apparatus of claim 2, wherein said apparatus is configured for performing the random access data write, at least in part, before the first information is sent.

18. The apparatus of claim 17, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes storing the at least portion of the fifth command in the additional memory.

19. The apparatus of claim 17, wherein said apparatus is configured such that the performing the random access data write, at least in part, includes causing the second information to be written to the NAND flash memory.

20. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read is one of a plurality of random access reads interleaved with a plurality of random access writes.

21. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read includes an arbitrary access data read.

22. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read includes an access in connection with at least one of an arbitrary time or an arbitrary address.

23. The apparatus of claim 1, wherein the apparatus is configured such that the random access data read is one of a plurality of random access reads interspersed with a plurality of random access writes.

24. The apparatus of claim 1, wherein the apparatus is configured such that the status allows a determination as to whether all of the first information has been written to the random access memory.

25. The apparatus of claim 1, wherein the apparatus is configured such that the status is communicated, in response to the status query, at an arbitrary time.

26. The apparatus of claim 1, wherein the apparatus is configured such that the status query is received via an access at an arbitrary time.

27. A system including the apparatus of claim 1, and further comprising the first bus and the processor.

28. The apparatus of claim 1, wherein the apparatus is configured such that the additional memory is part of the first circuit.

29. The apparatus of claim 1, wherein the apparatus is configured such that the random access memory includes dynamic random access memory.

30. The apparatus of claim 1, wherein the first bus, the second bus, and the third bus, include memory buses.

31. The apparatus of claim 1, wherein the apparatus is configured such that at least a portion of the first command is stored in at least one table in the additional memory.

32. The apparatus of claim 1, wherein the apparatus is configured such that the first command is a special command.

33. The apparatus of claim 1, wherein the apparatus is configured such that the first command enables DDR protocol-compliant communication of control information via the first bus for controlling the second circuit to effect one or more results that are undescribed in a specification of the DDR protocol.

34. The apparatus of claim 1, wherein the apparatus is configured such that the first command is one of a plurality of commands that allow an input of control information via the first bus.

35. The apparatus of claim 34, wherein the apparatus is configured such that the plurality of commands further includes at least one other command that is addressed to a particular random access memory location, that would otherwise not be the subject of standard addressing under the DDR protocol, for communicating the control information.

36. The apparatus of claim 1, wherein the apparatus is configured such that the first command is capable of being addressed to a particular random access memory location, such that the particular random access memory location is capable of standard addressing under a specification of a JEDEC standard, but is also capable of being used in a way that is undescribed in the specification of the JEDEC standard.

37. The apparatus of claim 1, wherein the apparatus is configured such that at least a part of the first data is the same as at least a part of the second data.

38. The apparatus of claim 1, wherein the apparatus is configured such that at least a part of the first data is the same as at least a part of the third data.

39. The apparatus of claim 1, wherein the apparatus is configured such that the additional memory includes logic memory.

40. An apparatus, comprising:

NAND flash memory;

random access memory;

additional memory;

first circuitry configured to receive DDR signals and output SATA signals, the first circuitry communicatively coupled to the additional memory, and further configured for use with a first bus operable with a DDR protocol; and

second circuitry configured to receive the SATA signals and output NAND flash signals, the second circuitry communicatively coupled to the first circuitry via a second bus, the second circuitry further communicatively coupled to the NAND flash memory via a third bus;

said first circuitry configured to;

receive a first command and associated first data via the first bus for causing at least a portion of a random access data write,

store at least a portion of the first command in the additional memory,

generate, in response to the first command, a second command and associated second data where the second data is based on at least a portion of the first data, and

send the second command to the second circuitry via the second bus;

said second circuitry configured to;

receive the second command from the first circuitry via the second bus,

generate, in response to the second command, a third command and associated third data where the third data is based on at least a portion of the second data, and

send the third command to the NAND flash memory via the third bus for causing information to be written to the NAND flash memory.

41. An apparatus, comprising:

NAND flash memory;

random access memory;

additional memory;

first circuitry configured to receive DDR signals and output SATA signals, the first circuitry communicatively coupled to the additional memory, and further configured for use with a first bus and a DDR protocol; and

second circuitry configured to receive the SATA signals and output NAND flash signals, the second circuitry communicatively coupled to the first circuitry via a second bus, the second circuitry further communicatively coupled to the NAND flash memory via a third bus, the second circuitry further communicatively coupled to the random access memory;

said apparatus configured such that;

said first circuitry;

receives a first command and associated first data via the first bus for causing at least a portion of a random access data read,

stores at least a portion of the first command in the additional memory,

generates, in response to the first command, a second command and associated second data that is based on at least a portion of the first data, and

sends the second command to the second circuitry via the second bus;

said second circuitry;

receives the second command from the first circuitry via the second bus,

generates, in response to the second command, a third command and associated third data that is based on at least a portion of the second data, and

sends the third command to the NAND flash memory via the third bus for causing first information in the NAND flash memory to be written to the random access memory;

said first circuitry;

receives a status query via the first bus for checking a status on the first information, and

allows, in response to the status query, the status to be checked on the first information;

said first circuitry;

receives a fourth command and associated fourth data via the first bus for causing the first information to be read from the random access memory, and

sends, in response to the fourth command, the first information from the random access memory to the processor via the first bus;

said first circuitry;

receives a fifth command and associated fifth data via the first bus for causing at least a portion of a random access data write,

stores at least a portion of the fifth command in the additional memory,

generates, in response to the fifth command, a sixth command and associated sixth data that is based on at least a portion of the fifth data, and

sends the sixth command to the second circuitry via the second bus; and

said second circuitry;

receives the sixth command from the first circuitry via the second bus,

generates, in response to the sixth command, a seventh command and associated seventh data that is based on at least a portion of the sixth data, and

sends the seventh command to the NAND flash memory via the third bus for causing second information to be written to the NAND flash memory.

42. The apparatus of claim 41, wherein the apparatus is configured such that the fifth command is received and the random access data write is performed at least in part, before the first information is sent.

43. The apparatus of claim 42, wherein the apparatus is configured such that the random access data write is performed at least in part, by storing the at least portion of the fifth command.

44. The apparatus of claim 42, wherein the apparatus is configured such that the random access data write is performed at least in part, by sending the sixth command.

45. The apparatus of claim 42, wherein the apparatus is configured such that the random access data write is performed at least in part, by sending the seventh command.

46. The apparatus of claim 42, wherein the apparatus is configured such that the random access data write is performed at least in part, by the second information being written to the NAND flash memory.

47. The apparatus of claim 41, wherein the apparatus is configured such that the fifth command is received and the random access data write is performed at least in part, before the status is allowed to be checked.

48. The apparatus of claim 47, wherein the apparatus is configured such that the random access data write is performed at least in part, by storing the at least portion of the fifth command.

49. The apparatus of claim 47, wherein the apparatus is configured such that the random access data write is performed at least in part, by sending the sixth command.

50. The apparatus of claim 47, wherein the apparatus is configured such that the random access data write is performed at least in part, by sending the seventh command.

51. The apparatus of claim 47, wherein the apparatus is configured such that the random access data write is performed at least in part, by the second information being written to the NAND flash memory.

52. The apparatus of claim 41, wherein the apparatus is configured such that the fifth command is received and the random access data write is performed at least in part, before the third command is sent.

53. The apparatus of claim 52, wherein the apparatus is configured such that the random access data write is performed at least in part, by storing the at least portion of the fifth command.

54. The apparatus of claim 52, wherein the apparatus is configured such that the random access data write is performed at least in part, by sending the sixth command.

55. The apparatus of claim 52, wherein the apparatus is configured such that the random access data write is performed at least in part, by sending the seventh command.

56. The apparatus of claim 52, wherein the apparatus is configured such that the random access data write is performed at least in part, by the second information being written to the NAND flash memory.

57. The apparatus of claim 41, wherein the apparatus is configured such that the fifth command is received and the random access data write is performed at least in part, before the second command is generated.

58. The apparatus of claim 57, wherein the apparatus is configured such that the random access data write is performed at least in part, by storing the at least portion of the fifth command.

59. The apparatus of claim 57, wherein the apparatus is configured such that the random access data write is performed at least in part, by sending the sixth command.

60. The apparatus of claim 57, wherein the apparatus is configured such that the random access data write is performed at least in part, by sending the seventh command.

61. The apparatus of claim 57, wherein the apparatus is configured such that the random access data write is performed at least in part, by the second information being written to the NAND flash memory.

62. A system, comprising:

a memory sub-system, including;

NAND flash memory,

random access memory,

additional memory,

first circuitry configured to receive DDR signals and output SATA signals, the first circuitry communicatively coupled to the additional memory, and further configured for being communicatively coupled to a first bus for use with a DDR protocol, and

second circuitry configured to receive the SATA signals and output NAND flash signals, the second circuitry communicatively coupled to the first circuitry via a second bus, the second circuitry further communicatively coupled to the NAND flash memory via a third bus, the second circuitry further communicatively coupled to the random access memory; and

a driver for cooperating with a processor to control the memory sub-system;

said system configured such that;

said driver causes a first command and associated first data to be sent from the processor to the first circuitry via the first bus for causing at least a portion of a random access data read;

said first circuitry;

receives the first command from the processor via the first bus,

stores at least a portion of the first command in the additional memory,

generates, in response to the first command, a second command and associated second data that is based on at least a portion of the first data, and

sends the second command to the second circuitry via the second bus;

said second circuitry;

receives the second command from the first circuitry via the second bus,

generates, in response to the second command, a third command and associated third data that is based on at least a portion of the second data, and

sends the third command to the NAND flash memory via the third bus for causing first information in the NAND flash memory to be written to the random access memory;

said driver causes a status query to be sent from the processor to the first circuitry via the first bus for checking a status on the first information;

said first circuitry;

receives the status query from the processor via the first bus, and

allows, in response to the status query, the status to be checked on the first information;

said driver causes a fourth command and associated fourth data to be sent from the processor to the first circuitry via the first bus for causing the first information to be read from the random access memory;

said first circuitry;

receives the fourth command from the processor via the first bus, and

sends, in response to the fourth command, the first information from the random access memory to the processor via the first bus;

said driver causes a fifth command and associated fifth data to be sent from the processor to the first circuitry via the first bus for causing at least a portion of a random access data write;

said first circuitry;

receives the fifth command from the processor via the first bus,

stores at least a portion of the fifth command in the additional memory,

generates, in response to the fifth command, a sixth command and associated sixth data that is based on at least a portion of the fifth data, and

sends the sixth command to the second circuitry via the second bus;

said second circuitry;

receives the sixth command from the first circuitry via the second bus,

generates, in response to the sixth command, a seventh command and associated seventh data that is based on at least a portion of the sixth data, and

sends the seventh command to the NAND flash memory via the third bus for causing second information to be written to the NAND flash memory.

63. The system of claim 62, wherein the system is configured such that:

said driver causes a second status query to be sent from the processor to the first circuitry via the first bus for checking a status on the second information;

said first circuitry;

receives the second status query from the processor via the first bus, and

allows, in response to the second status query, the status to be checked on the second information.

64. An apparatus, comprising:

NAND flash memory;

random access memory;

additional memory;

first circuitry configured for receiving DDR signals and outputting SATA signals, the first circuitry communicatively coupled to the additional memory, and further configured for being communicatively coupled to a first bus for use with a DDR protocol; and

second circuitry configured for receiving the SATA signals and outputting NAND flash signals, the second circuitry communicatively coupled to the first circuitry via a second bus, the second circuitry further communicatively coupled to the NAND flash memory via a third bus, the second circuitry further communicatively coupled to the random access memory;

said first circuitry configured for receiving, from a processor via the first bus, a read-related command including read-related data for causing at least a portion of a random access data read;

said first circuitry configured for storing at least a portion of the read-related command in the additional memory;

said first circuitry configured for, as a result of the read-related command being stored in the additional memory, generating a read-related corresponding command including at least a portion of the read-related data;

said first circuitry configured for sending, to the second circuitry via the second bus, the read-related corresponding command;

said second circuitry configured for, as a result of the receipt of the read-related corresponding command, generating an additional read-related corresponding command including at least a portion of the read-related data;

said second circuitry configured for sending, to the NAND flash memory via the third bus, the additional read-related corresponding command for causing particular data in the NAND flash memory to be written to the random access memory;

said first circuitry configured for, after a read-related status check on the apparatus to determine whether the particular data has been written to the random access memory, receiving, from the processor via the first bus, a read command to read the particular data written to the random access memory.

65. The system of claim 64, wherein:

said first circuitry is configured for receiving from the processor via the first bus, a write-related command including write-related data for causing at least a portion of a random access data write;

said first circuitry is configured for storing at least a portion of the write-related command in the additional memory;

said first circuitry is configured for, as a result of the write-related command being stored in the additional memory, generating a write-related corresponding command including at least a portion of the write-related data;

said first circuitry is configured for sending, to the second circuitry via the second bus, the write-related corresponding command for causing certain data to be written to the random access memory;

said second circuitry is configured for, as a result of the receipt of the write-related corresponding command, generating an additional write-related corresponding command including at least a portion of the write-related data; and

said second circuitry is configured for sending, to the NAND flash memory via the third bus, the additional write-related corresponding command for causing the certain information to be written to the NAND flash memory after the certain data is written to the random access memory.

66. The system of claim 65, wherein said first circuitry is configured for, allowing a write-related status check on the apparatus to determine whether the certain data has been written to the NAND flash memory.

67. An apparatus, comprising:

NAND flash memory;

random access memory;

additional memory;

first means for receiving DDR signals via a first bus for use with a DDR protocol; and

second means for receiving SATA signals via a second bus, and outputting NAND flash signals via a third bus;

said first means for;

receiving a first command and associated first data via the first bus for causing at least a portion of a random access data read,

storing at least a portion of the first command in the additional memory,

generating, in response to the first command, a second command and associated second data that is based on at least a portion of the first data, and

sending the second command via the second bus;

said second means for;

receiving the second command via the second bus,

generating, in response to the second command, a third command and associated third data that is based on at least a portion of the second data, and

sending the third command to the NAND flash memory via the third bus for causing first information in the NAND flash memory to be written to the random access memory;

said first means for;

receiving a status query via the first bus for checking a status on the first information, and

allowing, in response to the status query, the status to be checked on the first information;

said first means for;

receiving a fourth command and associated fourth data via the first bus for causing the first information to be read from the random access memory, and

sending, in response to the fourth command, the first information from the random access memory to a processor via the first bus.