Array substrate and manufacturing method thereof, and display device

• US 9,190,427 B2
• Filed: 12/02/2013
• Issued: 11/17/2015
• Est. Priority Date: 05/30/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Choi, Seungjin, Kim, Heecheol, Song, Youngsuk, Yoo, Seongyeol
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US14/347,451
• Publication Number:
  US 20140353690A1
• Time in Patent Office: 715 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate comprise a base substrate (11), a gate line, a data line, and a pixel region defined by intersection of the gate line and the data line, which are formed on the base substrate (11), wherein the pixel region comprises a thin film transistor, and the thin film transistor comprises a gate, a gate insulation layer, an active layer, a source and a drain, the pixel region further comprise: at least one groove (110), formed on a surface of the base substrate (11); a first electrode layer (12) comprising at least one first electrode bar (120), the first electrode bars (120) are disposed in the groove (110) and electrically connected with each other; and a second electrode layer (13) comprising at least one second electrode bar (130), wherein the second electrode bars (130) are disposed outside the groove (110) and electrically connected with each other. No overlapping between the common electrode and the pixel electrode can be achieved, so as to improve display quality of the display device.

Claims

1. An array substrate, comprising a base substrate, a gate line, a data line, and a pixel region defined by intersection of the gate line and the data line, which are formed on the base substrate, wherein the pixel region comprises a thin film transistor, and the thin film transistor comprises a gate, a gate insulation layer, an active layer, a source and a drain, wherein the pixel region further comprises:

at least one groove, formed on a surface of the base substrate;

a first electrode layer, comprising at least one first electrode bar, wherein the at least one first electrode bar is disposed in the corresponding groove and electrically connected with each other; and

a second electrode layer, comprising at least one second electrode bar, wherein the second electrode bar is disposed outside the groove and electrically connected with each other.

2. The array substrate according to claim 1, wherein the grooves formed on the base substrate are equispaced.

3. The array substrate according to claim 1, wherein a depth of the groove is greater than a thickness of the first electrode layer.

4. The array substrate according to claim 1, wherein the first electrode bar is disposed in each groove and the second electrode bar is disposed outside each groove.

5. The array substrate according to claim 1, wherein the gate insulation layer is disposed between the first electrode layer and the second electrode layer;

and

the first electrode layer is connected with the drain by a via hole in the gate insulation layer.

6. The array substrate according to claim 1, wherein the array substrate further comprises a passivation layer, and the gate insulation layer is disposed under the first electrode layer, and the passivation layer is disposed between the first electrode layer and the second electrode layer;

and

the first electrode layer is directly connected with the drain.

7. The array substrate according to claim 1, wherein the array substrate further comprises a passivation layer, and the passivation layer is disposed between the first electrode layer and the second electrode layer;

and

the second electrode layer is connected with the drain by a via hole in the passivation layer.

8. The array substrate according to claim 1, wherein the array substrate further comprises a passivation layer, and the gate insulation layer is disposed between the first electrode layer and the second electrode layer, and the passivation layer is disposed above the second electrode layer;

and

the second electrode layer is directly connected with the drain.

13. A display device, comprising the array substrate according to claim 1.

14. The array substrate according to claim 2, wherein the first electrode bar is disposed in each groove and the second electrode bar is disposed outside each groove.

15. The array substrate according to claim 3, wherein the first electrode bar is disposed in each groove and the second electrode bar is disposed outside each groove.

16. The array substrate according to claim 2, wherein the gate insulation layer is disposed between the first electrode layer and the second electrode layer;

and

the first electrode layer is connected with the drain by a via hole in the gate insulation layer.

17. The array substrate according to claim 3, wherein the gate insulation layer is disposed between the first electrode layer and the second electrode layer;

and

the first electrode layer is connected with the drain by a via hole in the gate insulation layer.

18. The array substrate according to claim 2, wherein the array substrate further comprises a passivation layer, and the gate insulation layer is disposed under the first electrode layer, and the passivation layer is disposed between the first electrode layer and the second electrode layer;

and

the first electrode layer is directly connected with the drain.

19. The array substrate according to claim 3, wherein the array substrate further comprises a passivation layer, and the gate insulation layer is disposed under the first electrode layer, and the passivation layer is disposed between the first electrode layer and the second electrode layer;

and

the first electrode layer is directly connected with the drain.

20. The array substrate according to claim 2, wherein the array substrate further comprises a passivation layer, and the passivation layer is disposed between the first electrode layer and the second electrode layer;

and

the second electrode layer is connected with the drain by a via hole in the passivation layer.

9. A method of manufacturing an array substrate, wherein the array substrate comprises a base substrate, a gate line, a data line and a thin film transistor formed on a non-display region of the base substrate, wherein the thin film transistor comprises a gate, a gate insulation layer, an active layer, a source and a drain, and the method comprises:

forming at least one groove on a surface of a display region of the base substrate;

forming a first transparent conductive thin film on the base substrate, and coating a first photoresist on the base substrate formed with the first transparent conductive thin film;

performing ashing treatment on the first photoresist to form a first photoresist pattern, the first photoresist pattern only covers a bottom of the groove;

performing etching process to remove a portion of the first transparent conductive thin film not covered by the first photoresist pattern;

performing lift-off process of photoresist to lift off the first photoresist pattern, so as to form a first electrode layer comprising at least one first electrode bar;

forming an insulation layer on the base substrate formed with the first electrode layer;

coating a second photoresist on the base substrate formed with the insulation layer, and performing ashing treatment on the second photoresist to form a second photoresist pattern, the second photoresist pattern only covers a bottom of a groove in the insulation layer; and

forming a second transparent conductive thin film on the base substrate formed with the second photoresist pattern, and then removing the second photoresist pattern and a portion of the second transparent conductive thin film on the second photoresist pattern by a lift-off process of photoresist, so as to form a second electrode layer comprising at least one second electrode bar.

10. The method according to claim 9, wherein,

the insulation layer comprises at least one of the gate insulation layer and the passivation layer;

the first electrode layer is connected with the drain, or the second electrode layer is connected with the drain.

11. The method according to claim 9, wherein the grooves on the base substrate are equispaced.

12. The method according to claim 9, wherein a depth of the groove is greater than a thickness of the first electrode layer.