Low noise charge pump method and apparatus

• US 9,190,902 B2
• Filed: 02/18/2013
• Issued: 11/17/2015
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Kelly, Dylan J., Cable, James S.
• Primary Examiner(s): Wells, Kenneth B
• Application Number:
  US13/769,780
• Publication Number:
  US 20140055194A1
• Time in Patent Office: 1,002 Days
• Field of Search: 327/536, 363/59, 363/60
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and/or simplify charge pump designs over a wide range of charge pump architectures.

Claims

1. A capacitive energy transfer converter including:

(a) at least one capacitive charge pump controlled by at least one clock input signal, for providing an output voltage supply based upon a coupled source voltage;

(b) a clock circuit for generating a clock signal, the clock circuit including an active driver circuit configured to both source current to and sink current from the clock circuit and current limiter circuitry configured to limit the source current and the sink current so as to cause a voltage waveform of the clock signal to be substantially sine-like; and

(c) one or more capacitive coupling networks configured to capacitively couple the clock signal to the at least one capacitive charge pump as one such at least one clock input signal, wherein the capacitive coupling necessitates that the clock signal be substantially sine-like.

2. The capacitive energy transfer converter of claim 1, wherein the one or more capacitive coupling networks are configured such that the clock signal provides substantial charge to the output voltage of the at least one capacitive charge pump.

3. The capacitive energy transfer converter of claim 1, wherein the one or more capacitive coupling networks are configured such that the clock signal does not conduct substantial charge to the output voltage of the at least one capacitive charge pump.

4. The capacitive energy transfer converter of claim 1, wherein the clock circuit is configured as a current starved ring oscillator.

5. The capacitive energy transfer converter of claim 1, wherein the current limiter circuitry is configured to limit the source current and sink current to a substantially identical magnitude.

6. The capacitive energy transfer converter of claim 1, wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

7. The capacitive energy transfer converter of claim 1, wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit.

8. A capacitive energy transfer converter including:

(a) at least one capacitive charge pump controlled by at least one clock input signal, for providing an output voltage supply based upon a coupled source voltage; and

(b) a clock generating circuit configured to provide a substantially sine-like clock signal capacitively coupled, without conveying substantial transfer current, to the at least one capacitive charge pump as one such at least one clock input signal.

9. The capacitive energy transfer converter of claim 8, further including circuitry configured to reduce voltage change rates of the clock signal during both positive and negative transitions such that the clock signal is substantially sine-like and wherein the capacitive coupling of the clock signal necessitates that the clock signal be substantially sine-like.

10. The capacitive energy transfer converter of claim 8, further including circuitry in the clock generating circuit configured to limit currents in the generation of the clock signal.

11. The capacitive energy transfer converter of claim 8, wherein the clock signal from the clock generating circuit is a single-phase clock signal.

12. The capacitive energy transfer converter of claim 8, wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

13. The capacitive energy transfer converter of claim 8, wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit.

14. A capacitive energy transfer converter including:

(a) at least one capacitive charge pump controlled by at least one clock input signal, for providing an output voltage supply based upon a coupled source voltage; and

(b) a clock generating circuit configured to provide a clock signal to the at least one capacitive charge pump as one such at least one clock input signal, the clock generating circuit including active limiting circuitry for limiting a rate of voltage change of the clock signal during both positive transitions and negative voltage transitions such that the clock signal is substantially sine-like.

15. The capacitive energy transfer converter of claim 14, wherein the clock generating circuit further includes current limiter circuitry for limiting currents in the generation of the clock signal.

16. The capacitive energy transfer converter of claim 14, wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

17. The capacitive energy transfer converter of claim 14, wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit.

18. A capacitive energy transfer converter including:

(a) at least one capacitive charge pump controlled by at least one single-phase clock input signal, for providing an output voltage based upon a coupled source voltage;

(b) at least one clock signal generating circuit configured to provide a single-phase substantially sine-like clock signal coupled capacitively to the at least one capacitive charge pump as one such at least one single-phase clock input signal, the at least one clock signal generating circuit including;

(1) voltage rate limiter circuitry to limit a rate of voltage change for the generated single-phase substantially sine-like clock signal; and

(2) current limiter circuitry to limit source current and sink current in the generation of the single-phase clock signal; and

(c) capacitive coupling circuitry configured to couple the single-phase substantially sine like clock signal to each capacitive charge pump.

19. The capacitive energy transfer converter of claim 18, wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

20. The capacitive energy transfer converter of claim 18, wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit.

21. A capacitive energy transfer converter for generating an output supply within a monolithic integrated circuit by alternately transferring charge from a voltage source to a transfer capacitor and from the transfer capacitor to the output supply, including single-phase charge pump clock circuitry configured to:

(a) couple the transfer capacitor to the output supply during discharge periods via a transfer capacitor discharging switch under control of a single-phase substantially sine-like charge pump clock output that is capacitively coupled to a control node of the transfer capacitor discharging switch and substantially isolated from the transfer capacitor; and

(b) couple the transfer capacitor to the voltage source via a transfer capacitor charging switch, during charge periods that non-overlappingly alternate with the discharge periods, under control of the single-phase substantially sine-like charge pump clock output that is capacitively coupled to a control node of the transfer capacitor charging switch.

22. The capacitive energy transfer converter of claim 21, wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

23. A capacitive energy transfer converter including:

(a) at least one capacitive charge pump controlled by at least one single-phase clock input signal, for providing an output voltage supply based upon a coupled source voltage by alternately charging and discharging an associated transfer capacitor during non-overlapping periods in response to the single-phase clock signal; and

(b) a clock generating circuit including;

(1) a current-starved ring oscillator configured to provide a single-phase substantially sine-like clock signal to the at least one capacitive charge pump as one such at least one single-phase clock input signal; and

(2) active limiting circuitry for limiting a rate of voltage change of the single-phase substantially sine-like clock signal during both positive transitions and negative voltage transitions.

24. The capacitive energy transfer converter of claim 23, wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

25. The capacitive energy transfer converter of claim 23, wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit.

26. A capacitive energy transfer converter including:

(a) at least one capacitive charge pump controlled by at least one single-phase clock input signal, for providing an output voltage based upon a coupled source voltage;

(b) at least one single-phase clock signal generating circuit including a ring oscillator comprising an odd number of not more than three inverting driver sections cascaded sequentially in a ring such that each driver section has an output coupled to a next driver section input, wherein a first driver section is next after a last driver section and one of the driver section outputs constitutes a single-phase clock signal, and wherein each driver section includes limiter circuitry to limit a rate of voltage change at the driver section output so as to cause the single-phase clock signal to be substantially sine-like; and

(c) capacitive coupling circuitry coupled to at least one capacitive charge pump and to at least one single-phase clock signal generating circuit and configured to couple the single-phase clock signal of the at least one single-phase clock signal generating circuit to the at least one capacitive charge pump as one such at least one single-phase clock input signal without increasing a rate of voltage rise or fall of the single-phase clock signal.

27. The capacitive energy transfer converter of claim 26, wherein the capacitive coupling circuitry is configured such that the single-phase clock signal provides substantial charge to the output voltage of the at least one capacitive charge pump.

28. The capacitive energy transfer converter of claim 26, wherein the capacitive coupling circuitry is configured such that the clock signal does not conduct substantial charge to the output voltage of the at least one capacitive charge pump.

29. The capacitive energy transfer converter of claim 26, wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

30. The capacitive energy transfer converter of claim 26, wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit.

31. A capacitive energy transfer converter for generating an output voltage supply within a circuit, including:

(a) charge pump apparatus for generating an output voltage supply within a circuit, comprising;

(1) a transfer capacitor;

(2) one or more source switching devices disposed in series between the transfer capacitor and a voltage source; and

(3) a first output switching device having a first device area disposed between a first terminal of the transfer capacitor and the output voltage supply, and a second output switching device disposed between a common reference connection of the output voltage supply and a second terminal of the transfer capacitor opposite the first terminal of the transfer capacitor, having a second device area that is at least double the first device area; and

(b) a charge pump clock generating circuit configured to provide a single-phase charge pump clock output coupled to all of the source switching devices to cause conduction during charge periods and nonconduction during discharge periods for all of the source switching devices, the charge pump clock output further coupled to all of the output switching devices to cause nonconduction during the charge periods and conduction during the discharge periods for all of the output switching devices.

32. The capacitive energy transfer converter of claim 31, wherein at least two of the capacitive energy transfer converters are configured as a stack to obtain higher or lower voltages than the single capacitive energy transfer converter.

33. The capacitive energy transfer converter of claim 31, wherein the capacitive energy transfer converter is embodied within a monolithic integrated circuit.

34. A clock generating circuit configured to be coupled to a capacitive charge pump for controlling alternate charging and discharging of an associated transfer capacitor of the capacitive charge pump during non-overlapping periods, the clock generating circuit including:

(a) a current-starved ring oscillator configured to provide a single-phase clock signal to the capacitive charge pump; and

(b) active limiting circuitry for limiting a rate of voltage change of the single-phase clock signal during both positive transitions and negative voltage transitions.

35. The clock generating circuit of claim 34, wherein the clock generating circuit is embodied within a monolithic integrated circuit.

36. A clock generating circuit configured to be coupled to a capacitive charge pump for controlling alternate charging and discharging of an associated transfer capacitor of the capacitive charge pump during non-overlapping periods, the clock generating circuit configured to provide a single-phase substantially sine-like clock signal coupled capacitively to the capacitive charge pump, the clock signal generating circuit including:

(a) voltage rate limiter circuitry to limit a rate of voltage change for the generated single-phase substantially sine-like clock signal; and

(b) current limiter circuitry to limit source current and sink current in the generation of the single-phase substantially sine-like clock signal.

37. The clock generating circuit of claim 36, wherein the clock generating circuit is embodied within a monolithic integrated circuit.

38. A clock generating circuit configured to be coupled to a capacitive charge pump for controlling alternate charging and discharging of an associated transfer capacitor of the capacitive charge pump during non-overlapping periods, the clock generating circuit configured to provide a substantially sine-like clock signal for capacitively coupling, without conveying substantial transfer current, to the capacitive charge pump.

39. The clock generating circuit of claim 38, wherein the clock generating circuit is embodied within a monolithic integrated circuit.

40. A clock generating circuit configured to be coupled to a capacitive charge pump for controlling alternate charging and discharging of an associated transfer capacitor of the capacitive charge pump during non-overlapping periods, the clock generating circuit configured to provide a clock signal to the capacitive charge pump, the clock generating circuit including active limiting circuitry for limiting a rate of voltage change of the clock signal during both positive transitions and negative voltage transitions such that the clock signal is substantially sine-like.

41. The clock generating circuit of claim 40, wherein the clock generating circuit is embodied within a monolithic integrated circuit.