Stored data analysis

• US 9,195,608 B2
• Filed: 05/17/2013
• Issued: 11/24/2015
• Est. Priority Date: 05/17/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Friedlander, Robert R., Kraemer, James R., Ungar, David M.
• Primary Examiner(s): Tseng, Cheng-Yuan
• Assistant Examiner(s): Ahmed, Zubair
• Application Number:
  US13/896,461
• Publication Number:
  US 20140344548A1
• Time in Patent Office: 921 Days
• Field of Search: 711/206
• US Class Current: 1/1
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1018 involving hashing techniques, e.g. inverted page tables
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]

Abstract

A system comprises a hashing logic, which executes instructions to convert raw data into a first logical address and payload data, where the first logical address describes metadata about the payload data. A hardware translation unit executes instructions to translate the first logical address into a first physical address on a storage device. A hardware load/storage unit stores the first logical address and the payload data at the first physical address on the storage device. A hardware exclusive OR (XOR) unit compares two logical address vectors to derive a Hamming distance between the two logical address vectors. A hardware retrieval unit retrieves other payload data that is stored at a second physical address whose second logical address is within a predefined Hamming distance from the first logical address, thus allowing payload data from the two logical addresses to be grouped/associated with one another.

Claims

1. A system comprising:

a hashing logic, wherein the hashing logic executes instructions to convert raw data into a first logical address and payload data, wherein the first logical address describes metadata about the payload data;

a hardware translation unit, wherein the hardware translation unit executes instructions to translate the first logical address into a first physical address on a storage device;

a hardware load/storage unit, wherein the hardware load/storage unit stores the first logical address and the payload data at the first physical address on the storage device;

a hardware exclusive OR (XOR) unit, wherein the hardware XOR unit compares two logical address vectors to derive a Hamming distance between the two logical address vectors;

a hardware retrieval unit, wherein the hardware retrieval unit retrieves other payload data that is stored at a second physical address whose second logical address is within a predefined Hamming distance from the first logical address, and wherein a Hamming distance between the first logical address and the second logical address is derived by the hardware XOR unit;

an address vector converter, wherein the address vector converter is hardware that converts each “

zero”

bit in an address vector to a “

negative one”

bit to generate a converted address vector;

an address vector summer, wherein the address vector summer is hardware that sums each bit position from two or more address vectors to generate a summation address vector; and

a threshold logic, wherein the threshold logic compares the summation address vector to the first logical address, wherein a group of logical addresses whose summation address vector matches the first logical address is determined to address a storage location of a same class of payload data.

2. The system of claim 1, wherein the hardware XOR unit generates a Hamming distance between the first logical address and all logical addresses within the group of logical addresses whose summation address vector matches the first logical address, and wherein the hardware retrieval unit retrieves other payload data that are stored within a group of physical addresses that correspond to the group of logical addresses whose summation address vector matches the first logical address.

3. The system of claim 1, wherein the payload data quantitatively describes a commercial transaction.

4. The system of claim 1, wherein the payload data qualitatively describes a commercial transaction.

5. The system of claim 1, wherein the payload data qualitatively describes an entity.

6. The system of claim 1, wherein the hashing logic comprises one or more processors executing the instructions to convert the raw data into the first logical address and the payload data.

7. The system of claim 1, wherein the hardware translation logic, the hardware load/storage unit, the hardware XOR unit, and the hardware retrieval unit are all on a single silicon chip.

8. A method for analyzing stored data, the method comprising:

converting, by a hashing logic, raw data into a first logical address and payload data, wherein the first logical address describes metadata about the payload data;

translating, by a hardware translation unit, the first logical address into a first physical address on a storage device;

storing, by a hardware load/storage unit, the first logical address and the payload data at the first physical address on the storage device;

comparing, by a hardware exclusive OR (XOR) unit, a first address vector for the first logical address to a second address vector for a second logical address to derive a Hamming distance between the first and second logical addresses;

retrieving, by a hardware retrieval unit, other payload data that is stored at a second physical address whose second logical address is within a predefined Hamming distance from the first logical address, wherein a Hamming distance between the first logical address and the second logical address is derived by the hardware XOR unit;

converting, by an address vector converter, each “

zero”

bit in an address vector to a “

negative one”

bit to generate a converted address vector;

summing, by an address vector summer, each bit position from two or more address vectors to generate a summation address vector; and

comparing, by a threshold logic, the summation address vector to the first logical address, wherein a group of logical addresses whose summation address vector matches the first logical address is determined to address a storage location of a same class of payload data.

9. The method of claim 8, wherein the hardware XOR unit generates a Hamming distance between the first logical address and all logical addresses within the group of logical addresses whose summation address vector matches the first logical address, and wherein the hardware retrieval unit retrieves other payload data that are stored within a group of physical addresses that correspond to the group of logical addresses whose summation address vector matches the first logical address.

10. The method of claim 8, wherein the payload data quantitatively describes a commercial transaction.

11. The method of claim 8, wherein the payload data qualitatively describes a commercial transaction.

12. The method of claim 8, wherein the payload data qualitatively describes an entity.

13. The method of claim 8, wherein the hashing logic comprises one or more processors executing the instructions to convert the raw data into the first logical address and the payload data.

14. A computer program product for analyzing stored data, the computer program product comprising:

a non-transitory computer readable storage medium;

first program instructions to convert raw data into a first logical address and payload data, wherein the first logical address describes metadata about the payload data;

second program instructions to translate the first logical address into a first physical address on a storage device;

third program instructions to store the first logical address and the payload data at the first physical address on the storage device;

fourth program instructions to compare a first address vector for the first logical address to a second address vector for a second logical address to derive a Hamming distance between the first and second logical addresses;

fifth program instructions to retrieve other payload data that is stored at a second physical address whose second logical address is within a predefined Hamming distance from the first logical address, wherein a Hamming distance between the first logical address and the second logical address is derived by the hardware XOR unit;

sixth program instructions to convert each “

zero”

bit in an address vector to a “

negative one”

bit to generate a converted address vector;

seventh program instructions to sum each bit position from two or more address vectors to generate a summation address vector; and

eighth program instructions to compare the summation address vector to the first logical address, wherein a group of logical addresses whose summation address vector matches the first logical address is determined to address a storage location of a same class of payload data; and

wherein

the first, second, third, fourth, fifth, sixth, seventh, and eighth program instructions are stored on the non-transitory computer readable storage medium.

15. The computer program product of claim 14, wherein the hardware XOR unit generates a Hamming distance between the first logical address and all logical addresses within the group of logical addresses whose summation address vector matches the first logical address, and wherein the hardware retrieval unit retrieves other payload data that are stored within a group of physical addresses that correspond to the group of logical addresses whose summation address vector matches the first logical address.

16. The computer program product of claim 14, wherein the payload data quantitatively describes a commercial transaction.

17. The computer program product of claim 14, wherein the payload data qualitatively describes a commercial transaction.