FinFET extension regions

• US 9,196,712 B1
• Filed: 09/12/2014
• Issued: 11/24/2015
• Est. Priority Date: 09/12/2014
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Johnson, Jeffrey B., Lee, Kam-Leung, Hasanuzzaman, Mohammad
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US14/484,469
• Time in Patent Office: 438 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/10 with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 : with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device fabrication process includes forming a fin upon a semiconductor substrate and forming a gate upon the semiconductor substrate and upon and orthogonal to the fin, forming a source drain contacts by growing epitaxy material over the fin, forming a trench between the epitaxy material and a gate to expose an upper surface portion of the fin, doping the exposed fin portion to form an extension region, and activating the extension region. The semiconductor device may include the fin, gate, gate spacers upon sidewalls of the gate, a source drain contact adjacent to the gate spacers surrounding the fin, and doped extension regions within the fin below the gate spacers.

Claims

1. A semiconductor device fabrication process comprising:

forming a plurality of fins upon a semiconductor substrate;

forming a plurality of gates upon the semiconductor substrate and upon and orthogonal to the plurality of fins;

forming a plurality of source drain contacts by growing epitaxy material over the fins;

forming a trench between the epitaxially formed material and a gate to expose an upper surface of a fin region;

doping the fin region to form an extension region, and;

activating the extension region by annealing.

2. The semiconductor device fabrication process of claim 1, further comprising:

forming gate spacers upon sidewalls of the plurality of gates.

3. The semiconductor device fabrication process of claim 2, further comprising:

forming sacrificial spacers upon sidewalls of the gate spacers.

4. The semiconductor device fabrication process of claim 3, wherein forming sacrificial spacers further comprises:

depositing a liner layer upon the sidewalls of the gate spacers, and;

depositing a spacer layer upon the liner layer.

5. The semiconductor device fabrication process of claim 3, wherein forming the trench further comprises:

removing the sacrificial spacers upon the sidewalls of the gate spacers subsequent to the growing of epitaxy material.

6. The semiconductor device fabrication process of claim 1, wherein a lower surface of the extension region is above a lower surface of the plurality of fins prior to the annealing.

7. The semiconductor device fabrication process of claim 1, wherein a lower surface of the extension region is coplanar with a lower surface of the plurality of fins subsequent to the annealing.

8. The semiconductor device fabrication process of claim 1, wherein forming the plurality of gates upon the semiconductor substrate, further comprises:

forming a gate oxide layer upon the substrate and upon the plurality of fins;

forming gate material upon the gate oxide layer;

forming a gate cap upon the gate material, and;

removing portions of the gate oxide layer, gate material, and gate cap and retaining portions of the gate oxide layer, gate material, and gate cap to form the plurality of gates.

9. The semiconductor device fabrication process of claim 1, wherein the semiconductor substrate is a multilayered semiconductor substrate.

10. A semiconductor device fabrication process comprising:

forming a fin upon a semiconductor substrate;

forming a gate stack upon a semiconductor substrate and upon and orthogonal to the fin;

forming a gate spacer upon sidewalls of the gate stack;

forming a sacrificial spacer upon the gate spacer by depositing a liner layer and a spacer layer, removing portions of the liner layer and spacer layer, and retaining portions of the liner layer and portions of the spacer layer generally upon sidewalls of the gate spacer;

forming epitaxially grown material upon sidewalls of the fin;

forming a trench between the epitaxially grown material and the gate spacer to expose an upper surface of the fin by removing the sacrificial spacer;

forming extension regions by implanting ions within a fin region assessable by the trench, and;

forming replacement spacers upon sidewalls of the gate spacer and within the trench.

11. The semiconductor device fabrication process of claim 10, further comprising:

annealing the extension regions.