Circuits and methods using adjustable feedback for self-calibrating or self-testing a magnetic field sensor with an adjustable time constant
First Claim
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1. A magnetic field sensor, comprising:
- a magnetic field sensing element configured to generate a magnetic field signal in response to a magnetic field;
a primary circuit path coupled to receive and to process the magnetic field signal, the primary circuit path comprising a circuit parameter;
a clock frequency generator configured to generate a redistribution clock signal with a first redistribution clock frequency during a first time period and with a second different redistribution clock frequency during a second time period;
a feedback circuit path coupled at both ends to the primary circuit path and forming a feedback loop, wherein the feedback circuit path comprises;
a switched capacitor circuit coupled to receive the redistribution clock signal, the switched capacitor circuit forming an integrator, the switched capacitor circuit comprising a selectable unity gain frequency having a first unity gain frequency related to the first redistribution clock frequency during the first time period and having a second unity gain frequency related to the second redistribution clock frequency during the second time period, wherein the feedback circuit path is configured to generate an output signal coupled to calibrate the circuit parameter with first and second rates related to the first and second unity gain frequencies.
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Abstract
A magnetic field sensor includes a reference-field-sensing circuit channel that allows a self-test or a self-calibration of the circuitry of the magnetic field sensor. The self-test or the self calibration can have at least two different bandwidths that provide a respective at least two different rates of self-test or self-calibration.
133 Citations
50 Claims
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1. A magnetic field sensor, comprising:
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a magnetic field sensing element configured to generate a magnetic field signal in response to a magnetic field; a primary circuit path coupled to receive and to process the magnetic field signal, the primary circuit path comprising a circuit parameter; a clock frequency generator configured to generate a redistribution clock signal with a first redistribution clock frequency during a first time period and with a second different redistribution clock frequency during a second time period; a feedback circuit path coupled at both ends to the primary circuit path and forming a feedback loop, wherein the feedback circuit path comprises; a switched capacitor circuit coupled to receive the redistribution clock signal, the switched capacitor circuit forming an integrator, the switched capacitor circuit comprising a selectable unity gain frequency having a first unity gain frequency related to the first redistribution clock frequency during the first time period and having a second unity gain frequency related to the second redistribution clock frequency during the second time period, wherein the feedback circuit path is configured to generate an output signal coupled to calibrate the circuit parameter with first and second rates related to the first and second unity gain frequencies. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of adjusting a rate of a calibration or a rate of a self-test of a magnetic field sensor, comprising:
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generating, with a magnetic field sensing element, a magnetic field signal in response to a magnetic field; receiving and processing the magnetic field signal with a primary circuit path comprising a circuit parameter; generating a redistribution clock signal with a first redistribution clock frequency during a first time period and a with a second different redistribution clock frequency during a second time period; generating an output signal coupled to calibrate the circuit parameter with a feedback circuit path coupled at both ends to the primary circuit path and forming a feedback loop, wherein the feedback circuit path comprises; a switched capacitor circuit coupled to receive the redistribution clock signal, the switched capacitor circuit forming an integrator, the switched capacitor circuit comprising a selectable unity gain frequency having a first unity gain frequency related to the first redistribution clock frequency during the first time period and having a second unity gain frequency related to the second redistribution dock frequency during the second time period, wherein the output signal is operable to calibrate the circuit parameter with first and second rates related to the first and second unity gain frequencies. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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Specification