Switchable capacitive elements for programmable capacitor arrays

• US 9,209,784 B2
• Filed: 06/20/2013
• Issued: 12/08/2015
• Est. Priority Date: 04/27/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Iversen, Christian Rye, Granger-Jones, Marcus
• Primary Examiner(s): Le, Dinh
• Application Number:
  US13/922,337
• Publication Number:
  US 20130278317A1
• Time in Patent Office: 901 Days
• Field of Search: 327/308, 327/365, 327/427, 327/306, 455 78- 80, 333/81.R
• US Class Current: 1/1
• CPC Class Codes: H03H 21/0007 comprising switched capacitor [SC] devices
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

Switchable capacitive elements are disclosed, along with programmable capacitor arrays (PCAs). One embodiment of the switchable capacitive element includes a field effect transistor (FET) device stack, a first capacitor, and a second capacitor. The FET device stack is operable in an open state and in a closed state and has a plurality of FET devices coupled in series to form the FET device stack. The first capacitor and the second capacitor are both coupled in series with the FET device stack. However, the first capacitor is coupled to a first end of the FET device stack while the second capacitor is coupled to a second end opposite the first end of the FET device stack. In this manner, the switchable capacitive element can be operated without a negative charge pump, with decreased bias swings, and with a better power performance.

Claims

1. A switchable capacitive element comprising:

a field effect transistor (FET) device stack that is operable in an open state and in a closed state, the FET device stack comprising a plurality of FET devices coupled in series to form the FET device stack;

a first capacitor coupled to a first end of the FET device stack and being coupled in series with the FET device stack; and

a second capacitor coupled to a second end of the FET device stack opposite the first end of the FET device stack and being coupled in series with the FET device stack;

a third capacitor coupled in series with the first capacitor so that the first capacitor and the third capacitor provide a series capacitance;

wherein the second capacitor has an other capacitance, wherein the other capacitance of the second capacitor is higher than the series capacitance of the first capacitor and the third capacitor.

2. The switchable capacitive element of claim 1 wherein each of the plurality of FET devices comprises a drain contact, a source contact, and a gate contact, and wherein the switchable capacitive element further comprises:

a control circuit operably associated with the FET device stack, the control circuit being configured to;

bias the gate contact of each of the plurality of FET devices at a first voltage such that the FET device stack operates in the closed state, the first voltage being positive relative to a reference voltage; and

bias the gate contact of each of the plurality of FET devices at a second voltage and bias the drain contact and source contact of each of the plurality of FET devices at the first voltage, such that the FET device stack operates in the open state, the second voltage being lower than the first voltage and approximately non-negative relative to the reference voltage.

3. The switchable capacitive element of claim 2 wherein the second voltage is the same as the reference voltage.

4. The switchable capacitive element of claim 2, wherein the second voltage is non-negative relative to the reference voltage.

5. The switchable capacitive element of claim 2, wherein the control circuit is further configured to bias the drain contact and the source contact of each of the plurality of FET devices at the second voltage during the closed state of the FET device stack.

6. The switchable capacitive element of claim 5 wherein:

each of the plurality of FET devices is a type of FET device that is associated with a breakdown voltage and a pinch-off voltage; and

a magnitude of the first voltage can be estimated to be half of a magnitude of the breakdown voltage associated with the plurality of FET devices plus the pinch-off voltage associated with the plurality of FET devices.

7. The switchable capacitive element of claim 1 further comprising an input terminal and an output terminal, wherein:

the first capacitor and the third capacitor are coupled in series between the input terminal and the first end of the FET device stack; and

the second capacitor is coupled in series between the output terminal and the second end of the FET device stack.

8. The switchable capacitive element of claim 7 wherein:

each of the plurality of FET devices comprises a drain contact, a source contact, and a gate contact; and

the plurality of FET devices comprises at least a first FET device and a second FET device, the drain contact of the first FET device being at the first end of the FET device stack and the source contact of the second FET device being at the second end of the FET device stack.

9. The switchable capacitive element of claim 8 wherein:

the first capacitor and the third capacitor are coupled in series between the input terminal and the drain contact of the first FET device; and

the second capacitor is coupled in series between the source contact of the second FET device and the output terminal.

10. The switchable capacitive element of claim 7 wherein the input terminal is coupled to an upstream radio frequency (RF) circuit, and the output terminal is coupled to a downstream RF circuit such that the switchable capacitive element is coupled in series between the upstream RF circuit and the downstream RF circuit.

11. The switchable capacitive element of claim 7 wherein the input terminal is coupled to an upstream RF circuit and a downstream RF circuit, and the output terminal is grounded such that the switchable capacitive element is coupled in shunt between the upstream RF circuit and the downstream RF circuit.

12. The switchable capacitive element of claim 1 wherein:

the first capacitor has a first parasitic resistance;

the second capacitor has a second parasitic resistance; and

the third capacitor has a third parasitic resistance, wherein the second parasitic resistance is greater than the first parasitic resistance, and the second parasitic resistance is greater than the third parasitic resistance.

13. The switchable capacitive element of claim 1 further comprising:

an input terminal; and

an output terminal, wherein the output terminal is grounded.

14. A programmable capacitor array comprising:

a first switchable capacitive element, comprising;

a first field effect transistor (FET) device stack that is operable in an open state and in a closed state, the first FET device stack comprising a first plurality of FET devices coupled in series to form the first FET device stack;

a first capacitor coupled to a first end of the first FET device stack and coupled in series with the first FET device stack; and

a second capacitor coupled to a second end of the first FET device stack opposite the first end of the first FET device stack, and coupled in series with the first FET device stack; and

a third capacitor coupled in series with the first capacitor so that the first capacitor and the third capacitor provide a series capacitance;

wherein the second capacitor has an other capacitance, wherein the other capacitance of the second capacitor is higher than the series capacitance of the first capacitor and the third capacitor,

a second switchable capacitive element.

15. The programmable capacitor array of claim 14 wherein the first switchable capacitive element and the second switchable capacitive element are coupled in parallel and wherein the second switchable capacitive element comprises:

a second FET device stack that is operable in the open state and in the closed state, the second FET device stack comprising a second plurality of FET devices coupled in series to form the second FET device stack;

a fourth capacitor coupled to a third end of the second FET device stack and being coupled in series with the second FET device stack; and

a fifth capacitor coupled to a fourth end of the second FET device stack opposite the third end of the second FET device stack, and coupled in series with the second FET device stack.

16. The programmable capacitor array of claim 15 further comprising a control circuit wherein:

each of the first plurality of FET devices and each of the second plurality of FET devices comprises a drain contact, a source contact, and a gate contact; and

the control circuit is configured to;

bias the gate contact of each of the first plurality of FET devices at a first voltage such that the first FET device stack operates in the closed state;

bias the gate contact of each of the second plurality of FET devices at the first voltage such that the second FET device stack operates in the closed state, wherein the first voltage is positive relative to a reference voltage;

bias the gate contact of each of the first plurality of FET devices at a second voltage and bias the drain contact and the source contact of each of the first plurality of FET devices at the first voltage, such that the first FET device stack operates in the open state; and

bias the gate contact of each of the second plurality of FET devices at the second voltage and bias the drain contact and the source contact of each of the second plurality of FET devices at the first voltage, such that the second FET device stack operates in the open state, wherein the second voltage is lower than the first voltage and is substantially non-negative relative to the reference voltage.

17. The programmable capacitor array of claim 15, wherein a control circuit is configured to receive a control input that is indicative of a first selected state and a second selected state, wherein the first selected state is any one of either the closed state of the first FET device stack and the open state of the first FET device stack, and the second selected state is any one of either the closed state of the second FET device stack and the open state of the second FET device stack, the control circuit being configured to:

bias the gate contact of each of the first plurality of FET devices at a first voltage in response to the control input being received as indicative of the first selected state being the closed state of the first FET device stack;

bias the gate contact of each of the second plurality of FET devices at the first voltage in response to the control input being received as indicative of the second selected state being the closed state of the second FET device stack;

bias the gate contact of each of the first plurality of FET devices at a second voltage and bias the drain contact and the source contact of each of the first plurality of FET devices at the first voltage in response to the control input being received as indicative of the first selected state being the open state of the first FET device stack; and

bias the gate contact of each of the second plurality of FET devices at the second voltage and bias the drain contact and the source contact of each of the second plurality of FET devices at the first voltage in response to the control input being received as indicative of the first selected state being the open state of the second FET device stack.

18. The programmable capacitor array of claim 15 wherein the first switchable capacitive element further comprises:

a first input terminal;

a first output terminal;

the first capacitor and the third capacitor being coupled in series between the first input terminal and the first end of the first FET device stack; and

the second capacitor being coupled in series between the first output terminal and the second end of the first FET device stack.

19. The programmable capacitor array of claim 18 wherein the second switchable capacitive element further comprises:

a second input terminal;

a second output terminal;

the fourth capacitor being coupled in series between the second input terminal and the third end of the second FET device stack; and

the fifth capacitor being coupled in series between the second output terminal and the fourth end of the second FET device stack.

20. The programmable capacitor array of claim 19 wherein:

the first input terminal is coupled to an upstream radio frequency (RF) circuit and a downstream RF circuit and the first output terminal is grounded such that the first switchable capacitive element is coupled in shunt between the upstream RF circuit and the downstream RF circuit; and

the second input terminal is coupled to the upstream RF circuit and the downstream RF circuit and the second output terminal is grounded such that the second switchable capacitive element is coupled in shunt between the upstream RF circuit and the downstream RF circuit.