Vertical 4-way shared pixel in a single column with internal reset and no row select

• US 9,210,347 B2
• Filed: 01/03/2013
• Issued: 12/08/2015
• Est. Priority Date: 10/01/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yin, Zhiping, Fan, Xiaofeng, Li, Xiangli
• Primary Examiner(s): Velez, Roberto
• Assistant Examiner(s): Coleman, Stephen
• Application Number:
  US13/733,676
• Publication Number:
  US 20130128089A1
• Time in Patent Office: 1,069 Days
• Field of Search: 348/273, 348/308, 348/203.1, 348/268, 348/269, 348/272, 348/294
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A method and apparatus for reducing space and pixel circuit complexity by using a 4-way shared vertically aligned pixels in a same column. The at least four pixels in the pixel circuit share a reset transistor and a source follower transistor, can have a plurality of same colored pixels and a plurality of colors, but do not include a row select transistor.

Claims

1. A method of reading from a pixel circuit comprising a plurality of 4-way shared pixels in a column of a pixel array, said method comprising:

applying a first logic signal on a column line to turn on a reset transistor, the reset transistor, when turned on, causing a reset voltage to be applied on a shared storage region to which each pixel of the 4-way shared pixels is commonly electrically coupled;

applying a second logic signal on the column line to turn off the reset transistor, wherein the first and second logic signals are complimentary to each other;

applying a third logic signal pulse to a transistor connected to the column line to enable readout of signals applied by a source follower transistor to a sample and hold circuit via the column line, wherein the source follower transistor is directly connected to the column line and has a gate connected to the shared storage region;

reading out a pixel reset signal onto the column line from the source follower transistor while the third logic signal pulse is applied to the transistor connected to the column line;

transferring a pixel image signal to the shared storage area; and

reading out the pixel image signal onto the column line from the source follower transistor while the third logic signal pulse is applied to the transistor connected to the column line.

2. The method of claim 1, wherein the 4-way shared pixels are configured in respective sequential rows associated with the column line.

3. The method of claim 1, wherein the 4-way shared pixels in the column comprise a plurality of green pixels and a plurality of pixels of another color.

4. The method of claim 1, further comprising using a column pull up transistor to turn on and turn off the reset transistor connected to the column line.

5. The method of claim 1, wherein the first logic signal is a logic high signal, and the second logic signal is a logic low signal.

6. The method of claim 1, wherein said step of reading out the pixel reset signal further comprises:

applying a fourth logic pulse on a sample and hold reset signal control line to sample a reset signal on the column line.

7. The method of claim 6, wherein said step of reading out the pixel reset signal further comprises:

applying a fifth logic pulse on the sample and hold reset signal control line after the step of applying the fourth logic pulse.

8. The method of claim 6, wherein the fourth logic pulse is a logic high pulse.

9. The method of claim 6, wherein said step of reading out the pixel image signal further comprises:

applying a fifth logic pulse on a sample and hold image signal control line after applying the fourth logic pulse.

10. The method of claim 9, wherein the fifth logic pulse is a logic high pulse.

11. A method of reading from a pixel circuit comprising a plurality of at least four pixels in a column of a pixel array, each pixel including a photosensor and each pixel being commonly electrically coupled to a shared storage region, said method comprising:

turning on a reset transistor common to all of the plurality of at least four pixels by applying a first logic signal on a column line to which the gate of the reset transistor is coupled, causing a reset voltage to be applied on the shared storage region;

turning off the reset transistor by applying a second logic signal on the column line, wherein the first and second logic signals are complimentary to each other;

enabling the column line for readout by turning on a transistor connected to the column line to enable readout of signals applied by a source follower transistor to a sample and hold circuit via the column line, wherein the source follower transistor is directly connected to the column line and having has a gate connected to the shared storage region;

reading out the reset voltage from the pixel circuit through the source follower transistor;

transferring a pixel image signal from a photosensor of the pixel circuit to the shared storage region; and

reading out a pixel image signal onto the column line from the source follower transistor.

12. The method of claim 11, wherein each pixel of the plurality of pixels is configured in respective sequential rows of the first column.

13. The method of claim 11, wherein the plurality of pixels in the first column comprise a plurality of green pixels and a plurality of pixels of another color.

14. The method of claim 11, further comprising using a column pull up transistor on the column line to turn on and turn off the reset transistor connected to the column line.

15. The method of claim 11, further comprising using a sample and hold circuitry to sample and hold the reset voltage from the pixel circuit.

16. The method of claim 15, further comprising, after the reset voltage is read from the pixel circuit, transferring accumulated charge from a photosensor to the shared storage region.

17. The method of claim 16, further comprising using a sample and hold circuitry to sample and hold the accumulated charge from the photosensor.