Band gap reference circuit

• US 9,213,353 B2
• Filed: 03/13/2013
• Issued: 12/15/2015
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Siao, Yuan-Long
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US13/798,928
• Publication Number:
  US 20140266138A1
• Time in Patent Office: 1,007 Days
• Field of Search: 323313-317, 327538-543
• US Class Current: 1/1
• CPC Class Codes: G05F 3/16 being semiconductor devices
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

A band gap reference circuit is provided that includes a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), a fifth resistor (Rb), a capacitor (Ca), an operational amplifier A, a first field effect transistor (FET) (P1), a second FET (P2), a third FET (P3), a fourth FET (Pa), a first bipolar junction transistor (BJT) (Q1), a second BJT (Q2), and a third BJT (Q3). P3 and Rb are used to control Pa, which is configured to control current flow to a reference node, and thus a reference voltage (Vref) output by the band gap reference circuit. The band gap reference circuit is configured to output a substantially constant reference voltage and is less sensitive or susceptible to noise from a power supply. Additionally, the band gap reference circuit prevents Vref from overshooting when the band gap circuit is enabled.

Claims

1. A band gap reference circuit, comprising:

a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), and a fifth resistor (Rb);

a first operational amplifier (A) comprising a first input, a second input, and an amplifier output, the second input of amplifier A connected to R2 and R3;

a first field effect transistor (FET) (P1) comprising a first gate, a first source, and a first drain, the first drain of P1 connected to R1 and R2;

a second FET (P2) comprising a second gate, a second source, and a second drain;

a third FET (P3) comprising a third gate, a third source, and a third drain, the first gate, the second gate, and the third gate connected to the amplifier output of amplifier A;

a fourth FET (Pa) comprising a fourth gate, a fourth source, and a fourth drain, the fourth source connected to the second drain and Ra, the fourth gate connected to the third drain and Rb, the fourth drain connected to a first capacitor (Ca);

a first bipolar junction transistor (BJT) (Q1) comprising a first base, a first emitter, and a first collector, the first emitter connected to the first input of amplifier A and R1;

a second BJT (Q2) comprising a second base, a second emitter, and a second collector, the second emitter connected to R3; and

a third BJT (Q3) comprising a third base, a third emitter, and a third collector, the third emitter connected to Ra.

2. The band gap reference circuit of claim 1, at least one of Q1, Q2, or Q3 comprising a PNP configuration.

3. The band gap reference circuit of claim 1, where at least one of P1, P2, P3, or Pa is a p-type metal oxide semiconductor field effect transistor (pMOSFET).

4. The band gap reference circuit of claim 1, at least one of the first source of P1, the second source of P2, or the third source of P3 connected to a second supply voltage (Vdd).

5. The band gap reference circuit of claim 1, at least one of the first base of Q1, the second base of Q2, or the third base of Q3 connected to a first supply voltage (Vss).

6. The band gap reference circuit of claim 1, at least one of the first collector of Q1, the second collector of Q2, or the third collector of Q3 connected to a first supply voltage (Vss).

7. The band gap reference circuit of claim 1, the first input of amplifier A comprising an inverting input.

8. The band gap reference circuit of claim 1, the second input of amplifier A comprising a non-inverting input.

9. The band gap reference circuit of claim 1, R1 comprising a resistance substantially equal to a resistance of R2.

10. The band gap reference circuit of claim 1, the fourth drain of Pa connected to a reference voltage (Vref) line.

11. The band gap reference circuit of claim 1, Ca connected to a first supply voltage (Vss).

12. The band gap reference circuit of claim 1, Rb connected to a first supply voltage (Vss).

13. A band gap reference circuit, comprising:

a first resistor (R1), a second resistor (R2), a third resistor (R3), and a fourth resistor (Ra);

a first operational amplifier (A) comprising a first input, a second input, and an amplifier output, the second input of amplifier A connected to R2 and R3;

a first field effect transistor (FET) (P1), wherein;

a first source/drain region of P1 is connected to R1 and R2,

a second source/drain region of P1 is connected to a second supply voltage (Vdd), and

a gate of P1 is connected to the amplifier output; and

a second FET (P2), wherein;

a first source/drain region of P2 is connected to Vdd,

a second source/drain region of P2 is connected to Ra, and

a gate of P2 is connected to the amplifier output and the gate of P1.

14. The band gap reference circuit of claim 13, comprising:

a fourth FET (Pa), wherein;

a first source/drain region of Pa is connected to the second source/drain region of P2 and Ra, and

a second source/drain region of PA is connected to an output terminal of the band gap reference circuit.

15. The band gap reference circuit of claim 14, comprising:

a third FET (P3), wherein;

a first source/drain region of P2 is connected to Vdd,

a second source/drain region of P3 is connected to a gate of Pa, and

a gate of P3 is connected to the amplifier output, the gate of P1, and the gate of P2.

16. The band gap reference circuit of claim 15, comprising:

a fifth resistor (Rb), wherein;

the second source/drain region of P3 is connected to a first terminal of Rb; and

a second terminal of Rb is connected to a first supply voltage (Vss).

17. The band gap reference circuit of claim 14, comprising:

a first capacitor (Ca), a first terminal of the first Ca coupled to the second source/drain region of PA.

18. The band gap reference circuit of claim 17, a second terminal of the first Ca coupled to a first supply voltage (Vss).

19. The band gap reference circuit of claim 13, comprising:

a third BJT (Q3) connected to Ra.

20. A band gap reference circuit, comprising:

a first resistor (R1) and a second resistor (R2);

a first operational amplifier (A) comprising a first input, a second input, and an amplifier output, the second input of amplifier A connected to R2;

a first field effect transistor (FET) (P1), wherein;

a first source/drain region of P1 is connected to R1 and R2,

a second source/drain region of P1 is connected to a second supply voltage (Vdd), and

a gate of P1 is connected to the amplifier output;

a second FET (P2), wherein;

a first source/drain region of P2 is connected to Vdd, and

a gate of P2 is connected to the amplifier output and the gate of P1; and

a fourth FET (Pa), wherein;

a first source/drain region of Pa is connected to the second source/drain region of P2, and

a second source/drain region of PA is connected to an output terminal of the band gap reference circuit.