Barrier layer for FinFET channels

• US 9,214,555 B2
• Filed: 03/12/2013
• Issued: 12/15/2015
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Oxland, Richard Kenneth, van Dal, Mark, Holland, Martin Christopher, Vellianitis, Georgios, Passlack, Matthias
• Primary Examiner(s): Rodela, Eduardo A
• Assistant Examiner(s): Wall, Vincent
• Application Number:
  US13/795,786
• Publication Number:
  US 20140264592A1
• Time in Patent Office: 1,008 Days
• Field of Search: 257/192, 257/185, 438/44
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer.

Claims

1. An integrated circuit device, comprising:

a semiconductor body;

a gate region wrapped around three sides of a fin protruding outward from the semiconductor body;

a fin comprising;

a first epitaxial layer comprising a channel region;

a buffer layer located below the first epitaxial layer;

an insulating layer comprising an insulating material located between the first epitaxial layer and the buffer layer; and

an interface control layer arranged between the first epitaxial layer and the insulating layer, the interface control layer comprising a semiconductor composition having a bandgap larger than that of the first epitaxial layer.

2. The device of claim 1, wherein:

the first epitaxial layer has a first composition; and

the insulating layer has a second composition, that is different than the first epitaxial layer.

3. The device of claim 2 wherein the second composition is an aluminum oxide compound.

4. The device of claim 1, wherein the interface control layer comprises InP, GaAs, Si, or SiGe.

5. The device of claim 1, wherein:

the buffer layer has a thickness in the range from 20 to 300 nm;

the insulating layer has a thickness in the range from 2 to 50 nm; and

the interface control layer has a thickness in the range from 0.5 to 5 nm.

6. The device of claim 1, wherein the first epitaxial layer is a semiconductor material comprising Group III and Group V materials.

7. The device of claim 1, further comprising:

a field oxide arranged over the semiconductor body and below the gate region, and abutting opposing sidewalls of the buffer layer.

8. The device of claim 1, further comprising:

a gate insulating layer abutting an upper surface of the first epitaxial layer and separating the first epitaxial layer from the gate region.

9. An integrated circuit device, comprising:

a semiconductor body; and

a fin protruding outward from the semiconductor body, the fin including;

a channel layer comprising a channel region that laterally separates source and drain regions;

a current-blocking layer arranged directly below the channel layer, the current-blocking layer comprising an oxidized semiconductor material, which electrically isolates the channel layer from the semiconductor body; and

an interface control layer arranged between the channel layer and the current-blocking layer, the interface control layer having a bandgap larger than that of the channel layer.

10. The integrated circuit device of claim 9, wherein the channel layer comprises Si, SiGe, Ge, InAs, InGaAs, InSb, InAsSb, InGaSb, or combinations thereof.

11. The integrated circuit device of claim 9,

wherein the channel layer has a first composition;

and

wherein the current-blocking layer has a second composition, different than the first composition.

12. The integrated circuit device of claim 9, wherein the current-blocking layer includes aluminum (Al), gallium (Ga), arsenic (As), indium (In), antimony (Sb), or a combination thereof.

13. The integrated circuit device of claim 9, wherein the interface control layer is formed from a composition selected from the group consisting of:

indium phosphide (InP), gallium arsenide (GaAs), silicon (Si), silicon germanium (SiGe).

14. The integrated circuit device of claim 9, further comprising:

a buffer layer of semiconducting material arranged at a location that is between the channel layer and the current-blocking layer.

15. An integrated circuit device, comprising:

a semiconductor body;

a fin formed on the semiconductor body, and comprising;

a first epitaxial layer comprising a channel region;

a buffer layer located directly below the first epitaxial layer;

an insulating layer comprising an insulating material located vertically between the first epitaxial layer and the buffer layer;

an interface control layer arranged between the first epitaxial layer and the insulating layer, the interface control layer comprising a semiconductor composition having a bandgap larger than that of the first epitaxial layer.

16. The integrated circuit device of claim 15, wherein the insulating layer includes aluminum (Al), gallium (Ga), arsenic (As), indium (In), antimony (Sb), or a combination thereof.

17. The integrated circuit device of claim 15, wherein the interface control layer includes indium phosphide (InP), gallium arsenide (GaAs), silicon (Si), silicon germanium (SiGe), or a combination thereof.

18. The integrated circuit device of claim 15, wherein the insulating layer abuts the buffer layer and the interface control layer, and the interface control layer abuts the first epitaxial layer.