High-K dielectric structure for deep trench isolation

• US 9,224,740 B1
• Filed: 12/11/2014
• Issued: 12/29/2015
• Est. Priority Date: 12/11/2014
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Polvino, Sean M., Siddiqui, Shahab
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Dehne, Aaron
• Application Number:
  US14/566,929
• Time in Patent Office: 383 Days
• Field of Search: 438/386, 438/778, 438/785, 438/241, 438/239
• US Class Current: 1/1
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 2924/1436 Dynamic random-access memory [DRAM]
• CPC Class Codes: H10B 12/036 the capacitor extending under the transistor
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/33 the capacitor extending under the transistor
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench

Abstract

A method of deep trench isolation which includes: forming a semiconductor on insulator (SOI) substrate comprising a bulk semiconductor substrate, a buried insulator layer and a semiconductor layer on the buried insulator layer (SOI layer), one portion of the SOI substrate having a dynamic random access memory buried in the bulk semiconductor substrate (eDRAM) and a deep trench fin contacting the eDRAM and a second portion of the SOI substrate having an SOI fin in contact with the buried insulator layer; conformally depositing sequential layers of oxide, high-k dielectric material and sacrificial oxide on the deep trench fin and the SOI fin; stripping the sacrificial oxide over the SOI fin to expose the high-k dielectric material over the SOI fin; stripping the exposed high-k dielectric material over the SOI fin to expose the oxide layer over the SOI fin.

Claims

1. A method of deep trench isolation comprising:

forming a semiconductor on insulator (SOI) substrate comprising a bulk semiconductor substrate, a buried insulator layer and a semiconductor layer on the buried insulator layer (SOI layer), one portion of the SOI substrate having a dynamic random access memory buried in the bulk semiconductor substrate (eDRAM) and a deep trench fin contacting the eDRAM and a second portion of the SOI substrate having an SOI fin in contact with the buried insulator layer;

conformally depositing a layer of oxide on the deep trench fin and the SOI fin;

conformally depositing a layer of high-k dielectric material on the oxide;

conformally depositing a sacrificial oxide on the high-k dielectric material;

stripping the sacrificial oxide over the SOI fin to expose the high-k dielectric material over the SOI fin while avoiding stripping the sacrificial oxide over the deep trench fin contacting the eDRAM; and

stripping the exposed high-k dielectric material over the SOI fin to expose the oxide layer over the SOI fin.

2. The method of claim 1 further comprising, after the step of stripping the exposed high-k dielectric material:

stripping the sacrificial oxide over the deep trench fin while also stripping the oxide layer over the SOI fin;

depositing a capping layer over the deep trench fin and over the SOI fin.

3. The method of claim 2 wherein the capping layer is an oxide.

4. The method of claim 1 wherein the high-k dielectric material has a dielectric constant greater than 7.

5. The method of claim 1 wherein the high-k material is selected from the group consisting of HfO2 (hafnium oxide), HfSiO (hafnium silicon oxide), TiO2 (titanium oxide), La2O3 (lanthanum oxide) and Al2O3 (aluminum oxide) ZrO2 (zirconium oxide), Ta2O5 tantalum oxide), and other like oxides including perovskite-type oxides.

6. The method of claim 1 wherein the high-k material is doped by the addition of a dopant material to the high-k material.

7. The method of claim 6 wherein the dopant material is selected from the group consisting of lanthanum, aluminum and nitrogen.

8. The method of claim 1 wherein the deep trench fin is in direct contact with the eDRAM.

9. The method of claim 1 wherein the deep trench fin has a first portion in contact with the eDRAM and a second portion not in contact with the eDRAM such that the second portion of the deep trench fin is substantially devoid of the high-k material.

10. The method of claim 8 wherein only the first portion of the deep trench fin is in direct contact with the eDRAM.