Oxide semiconductor device

• US 9,224,870 B2
• Filed: 08/29/2014
• Issued: 12/29/2015
• Est. Priority Date: 07/31/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Ohara, Hiroki, Sasaki, Toshinari, Noda, Kosei, Kuwabara, Hideaki
• Primary Examiner(s): YUSHIN, NIKOLAY K
• Application Number:
  US14/472,618
• Publication Number:
  US 20140367680A1
• Time in Patent Office: 487 Days
• Field of Search: 257/43, 257/71, 257/72
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Claims

1. A semiconductor device comprising:

a gate wiring layer, a source wiring layer, and a power supply line;

a first transistor;

a second transistor including a gate electrode, a source electrode, and a drain electrode;

a capacitor including a first electrode and a second electrode;

an insulating layer over the first transistor, the second transistor, and the capacitor; and

a pixel electrode layer over the insulating layer,

wherein the first transistor comprises;

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising a channel formation region overlapping with the gate electrode layer with the gate insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor layer, the oxide insulating layer including a first contact hole and a second contact hole, wherein the oxide insulating layer covers a periphery of the oxide semiconductor layer;

a source electrode layer over the oxide insulating layer, the source electrode layer electrically connected to the oxide semiconductor layer through the first contact hole of the oxide insulating layer;

a drain electrode layer over the oxide insulating layer, the drain electrode layer electrically connected to the oxide semiconductor layer through the second contact hole of the oxide insulating layer; and

wherein the source electrode layer of the first transistor overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the drain electrode layer of the first transistor overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the gate wiring layer includes the gate electrode layer of the first transistor,

wherein the source wiring layer includes the source electrode layer of the first transistor,

wherein the gate wiring layer intersects with the source wiring layer in a wiring intersection,

wherein in the wiring intersection, the gate insulating layer and the oxide insulating layer are provided between the gate wiring layer and the source wiring layer,

wherein the drain electrode layer of the first transistor is electrically connected to the first electrode of the capacitor,

wherein the drain electrode layer of the first transistor is electrically connected to the gate electrode of the second transistor,

wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the power supply line,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the pixel electrode layer, and

wherein the oxide insulating layer comprises silicon.

2. The semiconductor device according to claim 1, wherein the second electrode of the capacitor is electrically connected to the power supply line.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

4. The semiconductor device according to claim 1, wherein a width in a channel length direction of the gate electrode layer of the first transistor is smaller than a width in a channel length direction of the oxide semiconductor layer.

5. The semiconductor device according to claim 1,

wherein a width in a channel length direction of the gate electrode layer of the first transistor is larger than a width in a channel length direction of the oxide semiconductor layer, and

wherein an end surface of the gate electrode layer of the first transistor overlaps with the source electrode layer or the drain electrode layer of the first transistor with the gate insulating layer and the oxide insulating layer interposed therebetween.

6. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer of the first transistor are formed of a light-transmitting conductive film.

7. A display module comprising:

the semiconductor device according to claim 1; and

an FPC.

8. An electric apparatus comprising:

the semiconductor device according to claim 1; and

at least one of a battery, a speaker, and a microphone.

9. A semiconductor device comprising:

a gate electrode layer over a substrate;

a first electrode layer over the substrate;

an first insulating layer over the gate electrode layer and the first electrode layer;

an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer comprising a channel formation region overlapping with the gate electrode layer with the first insulating layer therebetween;

an oxide insulating layer over the oxide semiconductor layer and the first insulating layer, the oxide insulating layer including a first contact hole and a second contact hole, wherein the oxide insulating layer covers a periphery of the oxide semiconductor layer;

a first conductive layer over the oxide insulating layer, the first conductive layer electrically connected to the oxide semiconductor layer through the first contact hole of the oxide insulating layer;

a second conductive layer over the oxide insulating layer, the second conductive layer electrically connected to the oxide semiconductor layer through the second contact hole of the oxide insulating layer;

a second insulating layer over the first conductive layer and the second conductive layer; and

a pixel electrode layer over the second insulating layer, the pixel electrode layer electrically connected to one of the first conductive layer and the second conductive layer,

wherein the first conductive layer overlaps with a first end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the second conductive layer overlaps with a second end of the oxide semiconductor layer with the oxide insulating layer interposed therebetween,

wherein the one of the first conductive layer and the second conductive layer overlaps with the first electrode layer with the oxide insulating layer and the first insulating layer therebetween, and

wherein the oxide insulating layer comprises silicon.

10. The semiconductor device according to claim 9, further comprising:

a capacitor wiring layer,

wherein the capacitor wiring layer includes the first electrode layer.

11. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

12. The semiconductor device according to claim 9, wherein a width in a channel length direction of the gate electrode layer is smaller than a width in a channel length direction of the oxide semiconductor layer.

13. The semiconductor device according to claim 9,

wherein a width in a channel length direction of the gate electrode layer is larger than a width in a channel length direction of the oxide semiconductor layer, and

wherein an end surface of the gate electrode layer overlaps with the first conductive layer or the second conductive layer with the first insulating layer and the oxide insulating layer interposed therebetween.

14. The semiconductor device according to claim 9, wherein the first conductive layer and the second conductive layer are formed of a light-transmitting conductive film.

15. A display module comprising:

the semiconductor device according to claim 9; and

an FPC.

16. An electric apparatus comprising:

the semiconductor device according to claim 9; and

at least one of a battery, a speaker, and a microphone.