Method and system for controlling an interleaver

• US 9,225,464 B2
• Filed: 02/20/2007
• Issued: 12/29/2015
• Est. Priority Date: 04/17/1998
• Status: Expired due to Fees

• Current Assignee: AT&T Intellectual Property I LP (AT&T, Inc.)
• Original Assignee: AT&T Intellectual Property I LP (AT&T, Inc.)
• Inventors: Starr, Thomas J. J.
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US11/709,103
• Publication Number:
  US 20070162789A1
• Time in Patent Office: 3,234 Days
• Field of Search: 714/774, 714/701, 714/708
• US Class Current: 1/1
• CPC Class Codes: G06F 21/56 Computer malware detection or handling, e.g. anti-virus arrangements
• CPC Class Codes: H03M 13/2789 Interleaver providing variable interleaving, e.g. variable block sizes
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H03M 13/353 Adaptation to the channel
• CPC Class Codes: H03M 13/6508 Flexibility, adaptability, parametrability and configurability of the implementation
• CPC Class Codes: H04L 1/0001 Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04
• CPC Class Codes: H04L 1/0003 by switching between different modulation schemes
• CPC Class Codes: H04L 1/0015 characterised by the adaptation strategy
• CPC Class Codes: H04L 1/0021 in which the algorithm uses adaptive thresholds
• CPC Class Codes: H04L 1/0025 Transmission of mode-switching indication
• CPC Class Codes: H04L 1/0026 Transmission of channel quality indication
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0075 Transmission of coding parameters to receiver H04L1/0023 takes precedence
• CPC Class Codes: H04L 1/20 using signal quality detector

Abstract

Systems and Methods for controlling an interleaver are disclosed. Generally, a first and second signal are received, wherein the first and second signals are selected from the group consisting of a signal to noise ration signal, a data rate signal, and a bit error rate signal. An interleaver control signal is then generated based on the first and second signals.

Claims

1. A controller for an interleaver, comprising:

a processor; and

a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations, comprising;

receiving a first signal;

receiving a second signal; and

generating an interleaver control signal based on the first and second signals,

wherein the first signal comprises a signal to noise ratio signal, and

wherein the second signal is selected from a group consisting of a data rate signal and a bit error rate signal.

2. The controller of claim 1, wherein the operations further comprise determining whether the first signal exceeds a threshold.

3. The controller of claim 1, wherein the operations further comprise determining whether the first signal exceeds a value.

4. The controller of claim 1, wherein the operations further comprise determining whether the second signal exceeds a threshold.

5. The controller of claim 1, wherein the operations further comprise determining whether the second signal exceeds a value.

6. The controller of claim 1, further comprising an interleaver coupled with the processor, the interleaver being operative to receive the control signal.

7. The controller of claim 6, wherein the interleaver is operative to alter an interleaved signal in response to the interleaver control signal.

8. The controller of claim 6, wherein the interleaver is operative to alter an interleave depth of an interleaved signal in response to the interleaver control signal.

9. The controller of claim 1, wherein the first and second signals are distinct signals.

10. A method for controlling an interleaver, the method comprising:

receiving, by a system comprising a processor, a first signal;

receiving, by the system, a second signal; and

generating, by the system, an interleaver control signal based on the first and second signals,

wherein the first signal comprises a signal to noise ratio signal, and

wherein the second signal is selected from a group consisting of a data rate signal and a bit error rate signal.

11. The method of claim 10, further comprising:

determining whether the first signal exceeds a threshold.

12. The method of claim 10, further comprising:

determining whether the first signal exceeds a value.

13. The method of claim 10, further comprising:

determining whether the second signal exceeds a threshold.

14. The method of claim 10, further comprising:

determining whether the second signal exceeds a value.

15. The method of claim 10, further comprising:

transmitting the interleaver control signal to an interleaver.

16. The method of claim 15, further comprising:

altering an interleaved signal in response to the interleaver control signal.

17. The method of claim 15, further comprising:

altering an interleave depth of an interleaved signal in response to the interleaver control signal.

18. The method of claim 10, wherein the first and second signal is a signal to noise ratio signal.

19. The method of claim 10, wherein the second signal is a data rate signal or a bit error rate signal.