Compressing data from multiple reads for error control management in memory systems

• US 9,239,751 B1
• Filed: 03/15/2013
• Issued: 01/19/2016
• Est. Priority Date: 12/27/2012
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Chen, Xiaoheng, Tai, Ying Yu, Zhu, Jiangli, Jeon, Seungjune
• Primary Examiner(s): Abraham, Esaw
• Assistant Examiner(s): Ahmed, Enam
• Application Number:
  US13/831,686
• Time in Patent Office: 1,040 Days
• Field of Search: 714/763
• US Class Current: 1/1
• CPC Class Codes: G06F 11/085 using codes with inherent redundancy, e.g. n-out-of-m codes

Abstract

The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. Some implementations include a method of compressing a sequence of read data values into a bit-tuple of a predefined length to enable soft information decoding systems that use less power and/or less memory. In some implementations, the bit-tuple of a predefined length is produced using M single-bit buffer locations, where M corresponds to the predefined length of the bit-tuple. Some implementations utilize a collection of characterization vectors that include soft information values associated with the possible permutations of the bit-tuples. In turn, a sequence of bit-tuples is converted into a sequence of soft information values by retrieving a particular characterization vector, and selecting a respective soft information value from that characterization vector for each bit-tuple in the sequence.

Claims

1. A method of representing a N-bit binary sequence from a sequence of N memory read operations, the method comprising:

in response to M initial read operations in a sequence of N read operations that read from a single memory location,

populating the M single-bit buffer locations by setting each respective single-bit buffer location of the M single-bit buffer locations to a value corresponding to a read value obtained by a respective read operation of the M initial read operations; and

in response to the N−

M subsequent read operations, in accordance with a determination that the M single-bit buffer locations are in a corresponding predefined state after the M initial read operations, and at least one of the N−

M subsequent read operations produces a read value that is different from a first predefined read value,

updating the state of the M single-bit buffer locations to a state that indicates which read operation in the sequence of N read operations is the first read operation in said sequence to produce a read value that is different from the first predefined read value.

2. The method of claim 1, wherein M=┌

log₂ (N+1)┐

.

3. The method of claim 1, wherein for each read operation in the N−

M subsequent read operations that produces a read value equal to the first predefined read value, the method further comprises;

maintaining the predefined state of the M single-bit buffer locations.

4. The method of claim 1, wherein each read operation in the sequence of N read operations produces a read value equal to a binary 1 or 0.

5. The method of claim 1, wherein each of the sequence of N read operations includes applying a respective reading signal.

6. The method of claim 5, wherein each respective reading signal is a reading threshold voltage suitable for a flash memory.

7. The method of claim 6, wherein the reading threshold voltages used for the sequence of N read operations comprise a monotonically increasing or decreasing sequence of reading threshold voltages.

8. The method of claim 1, wherein populating the M single-bit buffer locations occurs on a per read basis.

9. The method of claim 1, wherein populating the M single-bit buffer locations in order occurs from a constituent least-significant-bit location to a constituent most-significant-bit location of the M single-bit buffer locations.

10. The method of claim 1, further comprising obtaining a corresponding soft information value for decoding the single memory location based on the state of the M single-bit buffer locations.

11. A method of representing a sequence of data values using a plurality of buffer locations, wherein there are fewer buffer locations than the total number of data values in the sequence, the method comprising:

for an initial sub-sequence of the data values, populating the plurality of buffer locations by setting each of the plurality of buffer locations based on a respective sequential one of the initial sub-sequence of data values;

updating the collective state of the plurality of buffer locations for each remaining data value in a remaining sub-sequence of the sequence of data values in sequential order by;

determining whether the plurality of buffer locations is in a first state;

overwriting the first state of the plurality of buffer locations in accordance with a determination that the plurality of buffer locations is in the first state and the remaining data value has a predefined first value; and

forgoing updating the collective state of the plurality of buffer locations in accordance with a determination that the plurality of buffer locations is not in the first state or the remaining data value does not have the predefined first value.

12. The method of claim 11, wherein the sequence of data values includes a N-bit binary sequence.

13. The method of claim 12, further comprising generating the N-bit binary sequence by performing a sequence of N read operations of a single memory location storing a single-bit value, wherein each read operation produces a binary 1 or 0.

14. The method of claim 13, wherein each of the sequence of N read operations includes applying a respective reading signal.

15. The method of claim 14, wherein each respective reading signal is a threshold voltage suitable for a flash memory.

16. The method of claim 15, wherein the threshold voltages used for the sequence of N read operations comprise a monotonically increasing or decreasing sequence of threshold voltages.

17. The method of claim 11, wherein each of the plurality of buffer locations is configured to store a single-bit binary value.

18. The method of claim 17, wherein one of the plurality of buffer locations is populated for each data value in the initial sub-sequence of the data values.

19. The method of claim 11, wherein the plurality of buffer locations includes M=┌

log₂ (N+1)┐

single-bit buffer locations for each N-bit binary sequence generated.

20. The method of claim 11, wherein setting each respective buffer location comprises sequentially writing one of the sequence of data values to a respective one of the plurality of buffer locations.

21. The method of claim 11, wherein the first state corresponds to the all-zero state, and updating the state of the plurality buffer locations comprises:

incrementing the all-zero state, in accordance with a determination that a respective data value of the remaining sub-sequence is binary 0, by adding to the all-zero state a binary number based on a corresponding sequence position of the respective data value.

22. The method of claim 21, wherein the binary number is equal to the corresponding sequence position minus ┌

log₂ (N+1)┐

.

23. The method of claim 11, wherein populating the plurality of buffer locations in order occurs from a constituent least-significant-buffer location to a constituent most-significant-buffer location of the plurality of buffer locations.

24. A device operable to compress a N-bit binary sequence, the N-bit binary sequence having an initial sub-sequence of M bits and a remaining sub-sequence of N−

M bits, the device comprising;

M single-bit buffer locations, wherein N is greater than M; and

a compression module configured to;

populate the M single-bit buffer locations by setting each respective single-bit buffer location to a corresponding value from the initial sub-sequence of M bits; and

update the state of the M single-bit buffer locations, in accordance with a determination that the populated M single-bit buffer locations are in a corresponding predefined state, to a state that indicates which bit in the remaining sub-sequence of N−

M bits is the first bit in the sub-sequence of N−

M bits to have a read value that is different from a first predefined value.

25. The device of claim 24, wherein the N-bit binary sequence is generated by a sequence of N read operations from a single memory location.

26. The device of claim 24, wherein the number of single-bit buffer locations, M, is equal to ┌

log₂ (N+1)┐

.

27. The device of claim 24, wherein the compression module is further configured to sequentially evaluate each bit of the remaining sub-sequence of N−

M bits by;

determining whether the M single-bit buffer locations are in the predefined state;

determining whether the bit under evaluation has a read value equal to the first predefined value; and

maintaining the predefined state of the M single-bit buffer locations in response to a positive determination that the M single-bit buffer locations are in the predefined state and the bit under evaluation has a read value equal to the first predefined value.

28. A device operable to compress a sequence of data values, the device comprising:

a plurality of buffer locations, wherein there are fewer buffer locations than the total number of data values in the sequence;

a compression module configured to;

populate each of the plurality of buffer locations by setting each buffer location to a corresponding value from an initial sub-sequence of sequence of data values; and

update the collective state of the plurality buffer locations for each data value of a remaining sub-sequence of the sequence of data values in sequential order by determining whether the plurality of buffer locations is in a first state;

overwriting the first state;

overwriting the first state of the plurality of buffer locations in accordance with a determination that the plurality of buffer locations is in the first state and the remaining data value has a predefined first value;

and

forgoing updating the collective state of the plurality of buffer locations in accordance with a determination that the plurality of buffer locations is not in the the first state or the remaining data value does not have the predefined first value.