Instructions to perform JH cryptographic hashing
First Claim
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1. A method of performing a JH process in a computer processor, comprising:
- storing JH state bits are stored in a plurality of registers before executing instructions of a first type;
decoding instructions of the first type and a second type;
executing one or more instructions of the first type to perform substitution (S-Box) mappings and a linear (L) transformation on a JH state, byexecuting an instruction of a first type a first time to perform the S-Box mappings and the L transformation on a first component of the JH state stored in the first register, andexecuting an instruction of a first type a second time to perform the S-Box mappings and the L transformation on a second component of the JH state stored in the second register; and
executing one or more instructions of the second type to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed, wherein a format of an instruction of the first type includes a first register operand to store half of a JH state and a format of an instruction of the second type includes second and third register operands to hold results of execution of instructions of the first type.
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Abstract
A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
8 Citations
19 Claims
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1. A method of performing a JH process in a computer processor, comprising:
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storing JH state bits are stored in a plurality of registers before executing instructions of a first type; decoding instructions of the first type and a second type; executing one or more instructions of the first type to perform substitution (S-Box) mappings and a linear (L) transformation on a JH state, by executing an instruction of a first type a first time to perform the S-Box mappings and the L transformation on a first component of the JH state stored in the first register, and executing an instruction of a first type a second time to perform the S-Box mappings and the L transformation on a second component of the JH state stored in the second register; and executing one or more instructions of the second type to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed, wherein a format of an instruction of the first type includes a first register operand to store half of a JH state and a format of an instruction of the second type includes second and third register operands to hold results of execution of instructions of the first type. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An apparatus comprising:
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a plurality of data registers, wherein the plurality of data registers comprise a register to store a first half of JH state bits and a register to store a second half of the JH state bits; and an execution unit coupled with the plurality of the data registers, to execute one or more instructions of a first type to perform S-Box mappings and a linear (L) transformation on a JH state and one or more instructions of a second type to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed, wherein a format of an instruction of the first type includes a first register operand to store half of a JH state and a format of an instruction of the second type includes second and third register operands to hold results of execution of instructions of the first type, wherein the execution unit to execute the instructions of the first type a first time to perform the S-Box mappings and the L transformation on the first half of the JH state bits and to execute the instructions of the first type a second time to perform the S-Box mappings and the L transformation on the second half of the JH state bits. - View Dependent Claims (8, 9, 10, 11)
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12. An article of manufacture comprising:
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a non-transitory machine-readable storage medium including one or more solid data storage materials, the machine-readable storage medium storing instructions, which when executed causes a processor to; store JH state bits are stored in a plurality of registers before executing instructions of a first type; decode instructions of the first type and a second type; execute one or more instructions of the first type to perform substitution (S-Box) mappings and a linear (L) transformation on a JH state, by executing an instruction of a first type a first time to perform the S-Box mappings and the L transformation on a first component of the JH state stored in the first register, and executing an instruction of a first type a second time to perform the S-Box mappings and the L transformation on a second component of the JH state stored in the second register; and execute one or more instructions of the second type to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed, wherein a format of an instruction of the first type includes a first register operand to store half of a JH state and a format of an instruction of the second type includes second and third register operands to hold results of execution of instructions of the first type. - View Dependent Claims (13, 14, 15)
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16. A system comprising:
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an interconnect; a processor coupled with the interconnect, the processor including a plurality of data registers, wherein the plurality of data registers comprise a register to store a first half of JH state bits and a register to store a second half of the JH state bits, and the processor to execute one or more instructions of a first type to perform S-Box mappings and a linear (L) transformation on a JH state and one or more instructions of a second type to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed, wherein a format of an instruction of the first type includes a first register operand to store half of a JH state and a format of an instruction of the second type includes second and third register operands to hold results of execution of instructions of the first type, wherein the processor to execute the instructions of a first type a first time to perform the S-Box mappings and the L transformation on the first half of the JH state bits and to execute the instructions of a first type a second time to perform the S-Box mappings and the L transformation on the second half of the JH state bits; and a dynamic random access memory (DRAM) coupled with the interconnect. - View Dependent Claims (17, 18, 19)
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Specification