Sense amplification circuits, output circuits, nonvolatile memory devices, memory systems, memory cards having the same, and data outputting methods thereof

• US 9,257,181 B2
• Filed: 03/22/2012
• Issued: 02/09/2016
• Est. Priority Date: 03/23/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Taesung, Im, Jaewoo
• Primary Examiner(s): NGUYEN, HIEN N
• Application Number:
  US13/427,019
• Publication Number:
  US 20120243342A1
• Time in Patent Office: 1,419 Days
• Field of Search: 365/189.05, 365/189.09, 365/203, 365/205, 365/207
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

An output circuit of a nonvolatile memory device includes a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage corresponding to data read from at least one memory cell, and the sense amplification circuit being further configured to connect the reference data line with a ground terminal during the sensing operation.

Claims

1. An output circuit comprising:

a plurality of page buffer latches configured to latch data read from a plurality of memory cells;

a plurality of sub data lines configured to receive voltages corresponding to the latched data in response to latch addresses;

a data line connected to the plurality of sub data lines;

a reference data line to which a current path is formed during a sensing operation; and

a sense amplification circuit configured to, during the sensing operation, sense a voltage difference between the reference data line and the data line, and to output data corresponding to the sensed voltage difference.

2. The output circuit of claim 1, further comprising:

a column selection circuit configured to connect the data line with the plurality of sub data lines sequentially in response to a plurality of column addresses.

3. The output circuit of claim 2, wherein the column selection circuit comprises:

a plurality of column selection transistors, each of the plurality of column selection transistors being configured to connect a sub data line from among the plurality of sub data lines with the data line in response to a column address from among the plurality of column addresses.

4. The output circuit of claim 2, wherein the reference data line is coupled to a load element having a load corresponding to a load of the data line.

5. The output circuit of claim 1, wherein the sense amplification circuit comprises:

a pre-charge circuit configured to pre-charge the reference data line and the data line;

a current path generator configured to form the current path to the reference data line after the reference data line and the data line are pre-charged; and

a differential sense amplifier configured to sense the voltage difference between the reference data line and the data line.

6. The output circuit of claim 5, wherein the pre-charge circuit comprises:

at least one first transistor configured to apply a power supply voltage to the reference data line and the data line in response to a pre-charge signal.

7. The output circuit of claim 5, wherein the current path generator electrically connects the reference data line to a ground terminal during the sensing operation.

8. The output circuit of claim 5, wherein the current path generator changes a voltage of the reference data line during the sensing operation.

9. The output circuit of claim 8, wherein the current path generator is configured to lower a voltage of the reference data line during the sensing operation, and wherein a slope of a voltage of the reference data line is less than a slope of a voltage of the data line when the latched data is indicative of a decrease in the voltage of the data line.

10. The output circuit of claim 9, wherein a variation in the voltage of the reference data line is less than a variation in the voltage of the data line.

11. The output circuit of claim 10, wherein, when performing the sensing operation, a variation in the voltage of the reference data line is between voltage values corresponding to the latched data.

12. The output circuit of claim 8, wherein the current path generator comprises:

at least one current path transistor connected between the reference data line and a path node, the at least one current path transistor having a gate configured to receive a trim code; and

a path forming transistor configured to connect the path node with a ground terminal in response to an inverted pre-charge signal.

13. The output circuit of claim 12, wherein the trim code varies according to an address for determining a physical location of a page buffer.

14. The output circuit of claim 12, wherein the trim code is implemented by at least one of an e-fuse, a laser fuse, and a register set.

15. The output circuit of claim 5, wherein the differential sense amplifier comprises:

a first transistor connected between a power terminal and an output node, the first transistor having a gate connected to an inverted output node;

a second transistor connected between the power terminal and the inverted output node, the second transistor having a gate connected to the output node;

a third transistor connected between the output node and a bias node, the third transistor having a gate connected to the inverted output node;

a fourth transistor connected between the inverted output node and the bias node, the fourth transistor having a gate connected to the output node; and

a fifth transistor configured to connect the bias node and a ground terminal during the sensing operation.

16. An output circuit comprising:

a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage corresponding to data read from at least one memory cell, and the sense amplification circuit being further configured to connect the reference data line with a ground terminal during the sensing operation.

17. The output circuit of claim 16, wherein the sense amplification circuit is configured to generate the output data while the reference data line is connected to the ground terminal.

18. The output circuit of claim 16, further comprising:

at least one page buffer latch configured to latch the data read from at least one memory cell.

19. The output circuit of claim 18, further comprising:

a column selection circuit configured to connect the data line with the at least one page buffer in response to a column address signal.

20. The output circuit of claim 16, wherein the sense amplification circuit comprises:

a differential sense amplifier configured to, during the sensing operation, compare the first voltage and the reference voltage, and to generate the output data based on the comparison; and

a current path generating circuit configured to connect the reference data line with the ground terminal during the sensing operation.

21. The output circuit of claim 20, wherein the sense amplification circuit further comprises:

a pre-charge circuit configured to pre-charge the reference data line and the data line in response to a pre-charge signal, wherein

the current path generating circuit is configured to connect the reference data line with the ground terminal based on a trim code and an inverted pre-charge signal.