Coreless packaging substrate and method of fabricating the same

• US 9,257,379 B2
• Filed: 03/12/2012
• Issued: 02/09/2016
• Est. Priority Date: 07/08/2011
• Status: Active Grant

• Current Assignee: Unimicron Technology Corporation
• Original Assignee: Unimicron Technology Corporation
• Inventors: Tseng, Tzyy-Jang, Ho, Chung-W.
• Primary Examiner(s): Willis, Tremesha S
• Application Number:
  US13/417,858
• Publication Number:
  US 20130008706A1
• Time in Patent Office: 1,429 Days
• Field of Search: 174/266, 174/250, 174/253, 174255-259, 174261-264
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A coreless packaging substrate is provided which includes: a circuit buildup structure having at least a dielectric layer, at least a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the lowermost one of the at least a dielectric layer, a plurality of metal bumps formed on the uppermost one of the at least a wiring layer, and a dielectric passivation layer formed on the surface of the uppermost one of the circuit buildup structure and the metal bumps, with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip is enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Claims

1. A coreless packaging substrate, comprising:

a circuit buildup structure having at least a dielectric layer, at least a wiring layer formed on the at least a dielectric layer, and a plurality of conductive elements formed in the dielectric layer and electrically connected to the at least a wiring layer;

a plurality of electrical pads embedded in a lowermost one of the at least a dielectric layer for electrically connecting part of the conductive elements, wherein the electrical pads are exposed from a surface of the lowermost one of the at least a dielectric layer;

a plurality of copper bumps formed on an uppermost one of the at least a wiring layer, and each having a copper column portion and a copper wing portion integrally formed on the copper column portion, wherein the copper wing portion of each of the copper bumps is greater in diameter than the copper column portion; and

a dielectric passivation layer formed on an uppermost one of the at least a dielectric layer, the uppermost one of the at least a wiring layer, and the copper bumps, with an entire top surface of the copper wing portion of each of the copper bumps exposed from the dielectric passivation layer,

wherein the exposed top surface of the copper wing portion of each of the copper bumps directly contacts and is electrically connected with solder bumps of a semiconductor chip,

the dielectric passivation layer is the same in width as the uppermost one of the at least a dielectric layer, and

the copper bumps are free from protruding from the dielectric passivation layer.

2. The coreless packaging substrate of claim 1, wherein the at least a wiring layer is embedded in the at least a dielectric layer.

3. The coreless packaging substrate of claim 1, wherein the conductive elements are conductive vias or conductive columns.

4. The coreless packaging substrate of claim 1, wherein exposed surfaces of the electrical pads are level with or lower than a surface of the lowermost one of the at least a dielectric layer.

5. The coreless packaging substrate of claim 1, wherein the exposed top surface of the copper wing portion of each of the copper bumps is even with a surface of the dielectric passivation layer.