Determining data retention time in a solid-state non-volatile memory

• US 9,263,158 B2
• Filed: 08/16/2013
• Issued: 02/16/2016
• Est. Priority Date: 08/16/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Prohofsky, Thomas R., Johnston, Darren E.
• Primary Examiner(s): NGUYEN, STEVE N
• Application Number:
  US13/969,049
• Publication Number:
  US 20150052416A1
• Time in Patent Office: 914 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes

Abstract

Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time.

Claims

1. A method comprising:

partitioning solid-state non-volatile memory cells of a non-volatile memory device into a plurality of units each individually allocatable for storage of user data;

allocating at least one of the plurality of units not storing user data as a control set;

storing user data from a host device to a first unit;

writing a test pattern to the control set;

reading the test pattern from the control set and identifying a total number of read errors;

determining a data retention time responsive to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern, the data retention time comprising an estimated time during which the memory device can store a set of data in a powered off condition and can successfully retrieve the data after being subsequently powered on;

obtaining system parameters comprising one or more of a current temperature value, a time stamp, a date stamp, and a total number of detected errors;

writing the parameters to the control set as a test log entry;

refreshing the user data in the first unit responsive to the determined data retention time; and

subsequently storing user data from the host device in the first unit.

2. The method of claim 1, further comprising communicating the determined data retention time to the host device.

3. The method of claim 1, further comprising subsequently performing the writing, reading and determining steps on the control set and using the data retention time obtained for the control set to refresh the user data stored in the first unit.

4. The method of claim 1, wherein the first unit and control set each comprise a garbage collection unit (GCU) comprising a plurality of erasure blocks of flash memory cells each of which are erased as a unit.

5. The method of claim 1, wherein the solid-state non-volatile memory cells comprises flash memory cells and each of the plurality of units comprises at least one erasure block of said flash memory cells.

6. The method of claim 1, wherein the total number of read errors is identified by applying an error correction code (ECC) to detect and correct at least one error in the readback data.

7. The method of claim 1, wherein the total number of read errors is identified by comparing the test pattern read back from the control set with an original copy of the test pattern.

8. The method of claim 1, wherein the refreshing data comprises identifying sets of user data stored in the array having a total storage time greater than or equal to the determined retention time, and copying the identified sets to a new location in the memory.

9. The method of claim 1, wherein the memory device is a solid-state drive (SSD) and the data retention time indicates an elapsed time during which applied external power can be removed from the SSD and, upon resumption of the applied external power, the SSD can retrieve the data from the memory cells.

10. The method of claim 1, wherein the data retention time is correlated to a specified temperature of the memory device.

11. An apparatus comprising:

an array of solid-state non-volatile memory cells arranged into addressable blocks;

a control circuit configured to direct storage of user data received from a host device to a first addressable block and to allocate at least one addressable block not storing user data as a control set;

an evaluation circuit configured to

write a test pattern to the control set, subsequently read the test pattern from the control set, identify a total number of read errors in the subsequently read test pattern, and determine a data retention time responsive to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern, the elapsed time interval comprising an elapsed duration of time of at least 30 minutes without an application of an intervening refresh operation to the memory cells during said interval;

obtain system parameters comprising one or more of a current temperature value, a time stamp, a date stamp, and a total number of detected errors; and

write the parameters to the control set as a test log entry;

the control circuit further configured to refresh the user data previously stored in the first addressable block responsive to the determined data retention time.

12. The apparatus of claim 11 characterized as a data storage device coupled to the host device, wherein the control circuit communicates the determined data retention time to the host device.

13. The apparatus of claim 11, wherein the evaluation circuit is further configured to subsequently write a second test pattern to the first addressable block, subsequently read the second test pattern from the first addressable block, identify a second total number of read errors in the subsequently read second test pattern, and determine a second data retention time responsive to the second total number of read errors and a second elapsed time interval between the writing of the test pattern and the reading of the test pattern, and wherein the control circuit is further configured to refresh the data previously stored in the second addressable block responsive to the second data retention time.

14. The apparatus of claim 11, wherein each addressable block comprises a garbage collection unit (GCU) comprising a plurality of erasure blocks of memory cells each of which are erased as a unit.

15. The apparatus of claim 11, wherein the solid-state non-volatile memory cells comprises flash memory cells and each of the first block and control set comprises at least one erasure block of said flash memory cells.

16. The apparatus of claim 11, wherein the total number of read errors is identified by applying an error correction code (ECC) to detect and correct at least one error in the readback data.

17. The apparatus of claim 11, wherein the total number of read errors is identified by comparing the test pattern read back from the control set with an original copy of the test pattern.

18. An apparatus comprising:

a flash memory array arranged into a plurality of garbage collection units (GCUs) erased and allocated as a unit;

a control circuit configured to direct storage of user data from a host device into a first GCU; and

an evaluation circuit which determines a current data retention time of the flash memory array by storing a test pattern in a second GCU during continued storage of the data in the first GCU and, at the conclusion of an elapsed time interval, identifies a total number of errors in a copy of the test pattern read back from the second GCU;

the control circuit further configured to obtain system parameters comprising one or more of a current temperature value, a time stamp, a date stamp, and a total number of detected errors;

write the parameters to the control set as a test log entry; and

communicate the current data retention time to a host device and to subsequently direct storage of user data from the host device to the second GCU.

19. The apparatus of claim 18, wherein the control circuit is further configured to direct a movement of a set of data from a first GCU to a third GCU of the flash memory array responsive to the set of data being stored in the first GCU for a period of time equal to or greater than the current data retention time.

20. The apparatus of claim 18, wherein the current data retention time comprises an elapsed period of time during which the flash memory array can store a set of data without an application of power to the array and return the set of data after being powered up at the conclusion of the elapsed period of time.