Method for fabricating array substrate of display using multiple photoresists

• US 9,263,480 B2
• Filed: 08/07/2013
• Issued: 02/16/2016
• Est. Priority Date: 04/26/2013
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Qin, Wei
• Primary Examiner(s): Jung, Michael
• Assistant Examiner(s): LIU, MIKKA H
• Application Number:
  US14/350,892
• Publication Number:
  US 20150214247A1
• Time in Patent Office: 923 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A fabricating method of an array substrate, an array substrate and a display device are provided. The array substrate includes a substrate; a plate electrode, a gate electrode, a gate line, a gate insulating film, semiconductor silicon islands, a source electrode, a drain electrode, a data line, a slit electrode formed on the substrate, and the substrate is also provided with a gate line through hole and a data line through hole. The gate electrode and the gate line include the first transparent conductive material and gate metal material stacked sequentially; the slit electrode is directly connected to the drain electrode; a second transparent conductive material is connected to the gate line through the gate line through hole; and connected to the data line through the data line through hole.

Claims

1. An array substrate comprising a substrate;

a plate electrode, a gate electrode, a gate line, a gate insulating film, a semiconductor silicon island, a source electrode, a drain electrode, a data line, a slit electrode formed on the substrate, and the substrate is also provided with a gate line through hole and a data line through hole, wherein

the gate electrode and the gate line comprise a first transparent conductive material and a gate metal material stacked sequentially;

the slit electrode is directly connected to the drain electrode;

a second transparent conductive material is connected to the gate line through the gate line through hole; and

connected to the data line through the data line through hole,

wherein the gate insulating film is arranged between the gate electrode and the semiconductor silicon island as well as between the plate electrode and the slit electrode.

2. The array substrate according to claim 1, wherein the plate electrode and the first transparent conductive material are arranged at the same layer and made of the same material.

3. The array substrate according to claim 1, wherein the slit electrode and the second transparent conductive material are arranged at the same layer and made of the same material.

4. The array substrate according to claim 1, wherein the source electrode and the drain electrode are arranged above the semiconductor silicon island, and the array substrate further comprise a semiconductor layer arranged below the data line and at the same layer with the semiconductor silicon island.

5. The array substrate according to claim 1, wherein the array substrate further comprise an insulation protecting structure above the source electrode, the drain electrode, the data line and the semiconductor silicon island.

6. A display device comprising an array substrate comprising a substrate, a plate electrode, a gate electrode, a gate line, a gate insulating film, a semiconductor silicon island, a source electrode, a drain electrode, a data line, a slit electrode formed on the substrate, and the substrate is also provided with a gate line through hole and a data line through hole, wherein

the gate electrode and the gate line comprise a first transparent conductive material and a gate metal material stacked sequentially;

the slit electrode is directly connected to the drain electrode;

a second transparent conductive material is connected to the gate line through the gate line through hole; and

connected to the data line through the data line through hole,

wherein the gate insulating film is arranged between the gate electrode and the semiconductor silicon island as well as between the plate electrode and the slit electrode.

7. The display device according to claim 6, wherein the plate electrode and the first transparent conductive material are arranged at the same layer and made of the same material.

8. The display device according to claim 6, wherein the slit electrode and the second transparent conductive material are arranged at the same layer and made of the same material.

9. The display device according to claim 6, wherein the source electrode and the drain electrode are arranged above the semiconductor silicon island, and the array substrate further comprises a semiconductor layer arranged below the data line and at the same layer with the semiconductor silicon island.

10. The display device according to claim 6, wherein the array substrate further comprises an insulation protecting structure above the source electrode, the drain electrode, the data line and the semiconductor silicon island.

11. A fabricating method of an array substrate, comprising following steps of:

forming a first transparent conductive film and a gate metal film sequentially, forming a first photoresist on the gate metal film, forming a pattern comprising a gate electrode, a gate line, and a plate electrode by a patterning process, and keeping a part of the first photoresist at a position corresponding to a gate line through hole;

forming a gate insulating film, a semiconductor film and a source-drain metal film sequentially;

removing the first photoresist at the position corresponding to the gate line through hole, and at the same time removing the gate insulating film, the semiconductor film and the source-drain metal film formed above the first photoresist at a position corresponding to the gate line through hole;

forming a second photoresist, and forming a pattern comprising a source electrode, a drain electrode, a data line and a semiconductor silicon island by a patterning process; and

forming a second transparent conductive film, a third photoresist, and forming a pattern comprising a slit electrode by a patterning process.

12. The fabricating method according to claim 11, wherein the step of forming the second transparent conductive film, the third photoresist and forming the pattern comprising the slit electrode by the patterning process comprises:

forming a pattern comprising the slit electrode and keeping the third photoresist at a position corresponding to the slit electrode, the gate line through hole and a data line through hole.

13. The fabricating method according to claim 12, wherein

after the step of forming the second transparent conductive film, the third photoresist and forming the pattern comprising the slit electrode by the patterning process, the fabricating method further comprises:

forming a passivation layer; and

removing the third photoresist at a position corresponding to the slit electrode, the gate line through hole, and the data line through hole, and at the same time, removing the passivation layer formed above the third photoresist at the position corresponding to the slit electrode, the gate line through hole and the data line through hole, so as to form a passivation layer pattern comprising the gate line through hole and the data line through hole.

14. The fabricating method according to claim 11, wherein the step of forming the first photoresist, forming a pattern comprising the gate electrode, the gate line, and the plate electrode by the patterning process and keeping the first photoresist at the position corresponding to the gate line through hole comprises steps of:

forming the first photoresist;

forming a first sub-photoresist at a position corresponding to the gate electrode and the gate line, forming a second sub-photoresist at a position corresponding to the plate electrode, and forming a third sub-photoresist at a position corresponding to the gate line through hole, by the patterning process; and

the third sub-photoresist has a thickness greater than that of the first sub-photoresist, and the thickness of the first sub-photoresist is greater than that of the second sub-photoresist;

removing the first transparent conductive film and the gate metal film not covered by the first sub-photoresist, the second sub-photoresist and the third sub-photoresist;

removing all the second sub-photoresist, and removing partial thickness of the first and third sub-photoresist;

removing the gate metal film corresponding to the second sub-photoresist so as to form a pattern comprising the plate electrode; and

removing the remaining first sub-photoresist to expose the pattern comprising the gate line and the gate electrode, and removing partial thickness of the third sub-photoresist and keeping the remaining third sub-photoresist.

15. The fabricating method according to claim 14, wherein the first sub-photoresist has a thickness of 1-4 μ

m, the second sub-photoresist has a thickness of 0.5-2 μ

m, and the third sub-photoresist has a thickness of 2-6 μ

m.

16. The fabricating method according to claim 11, wherein the step of forming the second photoresist, and forming a pattern comprising the source electrode, the drain electrode, the data line and the semiconductor silicon island comprises the steps of:

forming the second photoresist;

forming a fourth sub-photoresist at a position corresponding to the semiconductor silicon island, and forming a fifth sub-photoresist at a position corresponding to the source electrode, the drain electrode, the data line, the gate line through hole and the data line through hole; and

the fifth sub-photoresist has a thickness greater than that of the fourth sub-photoresist;

removing the semiconductor film and the source-drain metal film not covered by the fourth sub-photoresist and the fifth sub-photoresist;

removing all the fourth sub-photoresist and partial thickness of the fifth sub-photoresist;

removing the source-drain metal film and a part of the semiconductor film at a position corresponding to the fourth sub-photoresist, so as to form a pattern comprising the source electrode, the drain electrode, the data line and the semiconductor silicon island; and

removing the remaining fifth sub-photoresist.

17. The fabricating method according to claim 16, wherein the fourth sub-photoresist has a thickness of 0.5-1 μ

m, and the fifth sub-photoresist has a thickness of 1-2 μ

m.

18. The fabricating method according to claim 16, wherein the semiconductor film comprises an amorphous semiconductor film and a doped semiconductor film stacked sequentially, and the step of removing the source-drain metal film and a part of the semiconductor film at a position corresponding to the fourth sub-photoresist comprises:

removing the source-drain metal film and the doped semiconductor film at the position corresponding to the fourth sub-photoresist to expose the semiconductor film.