Apparatus, system, and method to adaptively optimize power dissipation and broadcast power in a power source for a communication device

• US 9,268,909 B2
• Filed: 10/15/2013
• Issued: 02/23/2016
• Est. Priority Date: 10/18/2012
• Status: Active Grant

• Current Assignee: Otsuka Pharmaceutical Company Limited (Otsuka Holdings Company Limited)
• Original Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Inventors: Jani, Nilay, Webb, Douglas, Withrington, Jonathan, Berkman, Jeffrey, Li, Haifeng
• Primary Examiner(s): Trinh, Sonny
• Application Number:
  US14/435,240
• Publication Number:
  US 20150294077A1
• Time in Patent Office: 861 Days
• Field of Search: 455/343.1, 455/343.2, 455/343.5, 455/571, 455/572, 455/574, 455/127.1, 320/107, 320/112, 320/134, 320/149, 320/114, 320/162
• US Class Current: 1/1
• CPC Class Codes: A61B 2560/0214 of power generation or supply
• CPC Class Codes: A61B 5/0537 Measuring body composition by impedance, e.g. tissue hydration or fat content
• CPC Class Codes: A61B 5/073 Intestinal transmitters
• CPC Class Codes: A61B 5/4848 Monitoring or testing the effects of treatment, e.g. of medication
• CPC Class Codes: A61B 5/6861 Capsules, e.g. for swallowing or implanting
• CPC Class Codes: G16H 40/40 for the management of medical equipment or devices, e.g. scheduling maintenance or upgrades
• CPC Class Codes: H04B 1/1607 Supply circuits converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04N 21/4436 Power management, e.g. shutting down unused components of the receiver power management in computer systems G06F1/3203; hibernate or awake process in computer systems G06F9/4418

Abstract

Provided is an apparatus, system, and method for stabilizing battery voltage of a battery device while optimizing power delivered to a receiver during communication of a broadcast packet. A logic circuit is configured to receive a broadcast packet having a predetermined number of bits for communication by a controller to a receiver located remotely from the controller, determine a number of cycles in which a sampled battery voltage is either greater than or less than or equal to a nominal battery voltage over a first subset of the predetermined number of bits of the broadcast packet and performs either a tune-up or a tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.

Claims

1. A method of stabilizing battery voltage of a battery device while optimizing power delivered to a receiver during communication of a broadcast packet, the method comprising:

receiving, by a logic circuit, a broadcast packet having a predetermined number of bits for communication by a controller to a receiver located remotely from the controller;

determining, by the logic circuit, a number of cycles in which a sampled battery voltage is either greater than or less than or equal to a nominal battery voltage over a first subset of the predetermined number of bits of the broadcast packet; and

performing a either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.

2. The method of claim 1, comprising:

performing a tune-up procedure when the sampled battery voltage is greater than the nominal battery voltage for more than one half of a total number of cycles counted; and

performing a tune-down procedure when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of a total number of cycles counted.

3. The method of claim 1, comprising determining, by the logic circuit, an operating mode, wherein the operating mode is either an X-bit multiple cycle operating mode or a Y-bit single cycle operating mode when the number of cycles in which the sampled battery voltage is not less than the nominal battery voltage for more than one half of a total number of cycles counted.

4. The method of claim 3, comprising determining, by the logic circuit, the number of cycles over a second subset of the predetermined number of bits of the broadcast packet in which the sampled battery voltage is greater than the nominal battery voltage.

5. The method of claim 4, comprising determining, by the logic circuit, whether the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet.

6. The method of claim 5, comprising:

waiting, by the logic circuit, for a subsequent broadcast packet when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet; and

performing the tune-up procedure when the number of cycles in which the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the second subset of the predetermined number of bits of the broadcast packet.

7. The method of claim 3, comprising determining, by the logic circuit, the number of cycles over a third subset of the predetermined number of bits of the broadcast packet in which the sampled battery voltage is greater than the nominal battery voltage.

8. The method of claim 7, comprising determining, by the logic circuit, whether the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet.

9. The method of claim 8, comprising:

waiting, by the logic circuit, for a subsequent broadcast packet when the sampled battery voltage is not greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet; and

performing the tune-up procedure when the number of cycles in which the sampled battery voltage is greater than the nominal battery voltage for more than one half of the cycles over the third subset of the predetermined number of bits of the broadcast packet.

10. The method of claim 1, wherein the tune-up procedure, comprises:

determining, by a logic circuit, whether a battery current as defined by a predetermined programmable value is at a maximum current limit;

determining, by the logic circuit, whether the battery current is at a minimum current limit when the battery current is less than the maximum current limit;

determining, by the logic circuit, whether a bit of the broadcast packet has a default pulse width when the battery current is at the minimum current limit; and

increasing the pulse width when the pulse width is not at the default pulse width; and

increasing the current limit when the pulse width is at the default pulse width.

11. The method of claim 10, comprising setting, by the logic circuit, the pulse width to the default pulse width when the battery current is not at the minimum current limit.

12. The method of claim 10, comprising:

determining, by the logic circuit, whether the pulse width is at a maximum pulse width when the battery current is at the maximum current limit; and

increasing, by the logic circuit, the pulse width when the pulse width is not at a maximum pulse width.

13. The method of claim 1, wherein the tune-down procedure, comprises:

determining, by a logic circuit, whether a battery current is at a minimum current limit;

determining, by the logic circuit, whether the battery current is at a maximum current limit when the battery current is less than the minimum current limit;

determining, by the logic circuit, whether a bit of the broadcast packet has a default pulse width when the battery current is at the maximum current limit; and

decreasing the pulse width when the pulse width is not at the default pulse width; and

decreasing the current limit when the pulse width is at the default pulse width.

14. The method of claim 13, comprising setting, by the logic circuit, the pulse width to the default pulse width when the battery current is not at the maximum current limit.

15. The method of claim 13, comprising:

determining, by the logic circuit, whether the pulse width is at a minimum pulse width when the battery current is at the minimum current limit; and

reducing, by the logic circuit, the pulse width when the pulse width is not at a minimum pulse width.

16. A logic circuit configured to stabilize battery voltage of a battery device while optimizing power delivered to a receiver during communication of a broadcast packet, the logic circuit comprising:

a processor configured to receive a broadcast packet having a predetermined number of bits for communication by a controller to a receiver located remotely from the controller;

determine a number of cycles in which a sampled battery voltage is either greater than or less than or equal to a nominal battery voltage over a first subset of the predetermined number of bits of the broadcast packet; and

perform a either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.

17. The logic circuit of claim 16, comprising:

a sample-and-hold circuit; and

an analog-to-digital converter, each coupled to the processor and the battery;

wherein the analog-to-digital converter samples the battery voltage to determine the sampled battery voltage.

18. The logic circuit of claim 17, comprising a battery coupled to the processor.

19. A communication system, comprising:

a processor configured to stabilize a voltage potential generated by an event indicator while optimizing power delivered to a receiver during communication of a broadcast packet by the event indicator to the receiver, the broadcast packet having a predetermined number of bits; and

an event indicator system with dissimilar metals positioned on opposite ends, wherein the event indicator is configured to generate a voltage potential when the dissimilar metals positioned on opposite ends dissolve in a conducting fluid;

wherein the processor is further configured to;

determine a number of cycles in which a sampled voltage potential is either greater than or less than or equal to a nominal voltage potential over a first subset of the predetermined number of bits of the broadcast packet;

perform a either a tune-up or tune-down procedure based on the number of cycles counted in which the sampled battery voltage is not equal to the nominal battery voltage for more than one half of a total number of cycles counted.

20. The communication system of claim 19, comprising:

a sample-and-hold circuit; and

an analog-to-digital converter, each coupled to the processor and the event indicator;

wherein the analog-to-digital converter is to sample the voltage potential to determine the sampled battery potential.