Instructions to perform JH cryptographic hashing in a 256 bit data path

• US 9,270,460 B2
• Filed: 12/22/2011
• Issued: 02/23/2016
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wolrich, Gilbert M., Yap, Kirk S., Gopal, Vinodh, Guilford, James D., Ozturk, Erdinc, Gulley, Sean M., Feghali, Wajdi K., Dixon, Martin G.
• Primary Examiner(s): Siddiqi, Mohammad A
• Application Number:
  US13/995,457
• Publication Number:
  US 20140205084A1
• Time in Patent Office: 1,524 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3893 controlled in tandem, e.g. multiplier-accumulator
• CPC Class Codes: H04L 9/14 using a plurality of keys or algorithms
• CPC Class Codes: H04L 9/3239 involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD

Abstract

A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

Claims

1. A method of performing a JH algorithm in a computer processor, comprising:

storing JH state bits in a plurality of registers;

decoding one or more instructions of a first and a second type;

executing one or more decoded instructions of the first type to perform S-Box mappings and a linear (L) transformation on a JH state, by

executing an instruction of the first type a first time to perform the S-Box mappings and the L transformation on a first component of the JH state stored in a first source register and store the results in a first destination register as first JH state results,

executing an instruction of the first type a second time to perform the S-Box mappings and the L transformation on a second component of the JH state stored in a second source register and store the results in a second destination register as second JH state results,

executing an instruction of the first type a third time to perform the S-Box mappings and the L transformation on a third component of the JH state stored in a third source register and store the results in a third destination register as third JH state results, and

executing an instruction of the first type a fourth time to perform the S-Box mappings and the L transformation on a fourth component of the JH state stored in a fourth source register and store the results in a fourth destination register as fourth JH state results, wherein an execution of an instruction of the first type performs 64 S-box mappings and 32 L transformations on a quarter of the JH state and a format of the instruction of the first type includes a source vector register operand, a destination vector register operand, and an operand to store constraints for S-box selection; and

executing one or more decoded instructions of the second type to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed by one or more instructions of the first type by retrieving JH state results from two of the destination registers and

performing a permutation function on the JH state results from the two destination registers.

2. The method of claim 1 wherein performing the permutation function comprises:

performing a first permutation function on the first JH state results and the second JH results;

performing a second permutation function on the third JH state results and the fourth JH results;

performing a third permutation function on the first JH state results and the second JH results; and

performing a fourth permutation function on the third JH state results and the fourth JH results.

3. An apparatus comprising:

a plurality of data registers;

a decode unit to decode instructions of a first and a second type; and

an execution unit coupled with the plurality of the data registers, to execute one or more instructions of the first type to perform S-Box mappings and a linear (L) transformation on a JH state and one or more instructions of the second type to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed by one or more instructions of the first type, wherein an execution of an instruction of the first type performs 64 S-box mappings and 32 L transformations on a quarter of the JH state and a format of the instruction of the first type includes a source vector register operand, a destination vector register operand, and an operand to store constraints for S-box selection,

wherein the execution unit to store the results of the first execution of the instruction of a first type in a first destination register as first JH state results, stores the results of the second execution of the instruction of a first type in a second destination register as second JH state results, stores the results of the third execution of the instruction of a first type of in a third destination register as third JH state results and stores the results of the fourth execution of the instruction of a first type of instruction in a fourth destination register as fourth JH state results,

wherein the execution unit to execute an instruction of a first type a first time to perform the S-Box mappings and the L transformation on a first component of the JH state stored in a first source register, a second time to perform the S-Box mappings and the L transformation on a second component of the JH state stored in a second source register, a third time to perform the S-Box mappings and the L transformation on a third component of the JH state stored in a third source register and a fourth time to perform the S-Box mappings and the L transformation on a fourth component of the JH state stored in a fourth source register, and

wherein the execution unit to retrieve JH state results from two of the destination registers and perform the permutation function on the JH state results from the two destination registers.

4. The apparatus of claim 3 wherein the execution unit to perform a first permutation function on the first JH state results and the second JH results, perform a second permutation function on the third JH state results and the fourth JH results, perform a third permutation function on the first JH state results and the second JH results, and perform a fourth permutation function on the third JH state results and the fourth JH results.

5. An article of manufacture comprising:

a non-transitory machine-readable storage medium including one or more solid data storage materials, the machine-readable storage medium storing instructions, which when executed causes a processor to;

store JH state bits in a plurality of registers;

decode one or more instructions of a first and a second type;

execute one or more instructions of the first type to perform S-Box mappings and a linear (L) transformation on a JH state, wherein an execution of an instruction of the first type performs 64 S-box mappings and 32 L transformations on a quarter of the JH state and a format of the instruction of the first type includes a source vector register operand, a destination vector register operand, and an operand to store constraints for S-box selection; and

execute one or more instructions of a second type to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed by

performing a first permutation function on the first JH state results and the second JH results,

performing a second permutation function on the third JH state results and the fourth JH results,

performing a third permutation function on the first JH state results and the second JH results, and

performing a fourth permutation function on the third JH state results and the fourth JH results.

6. A method of performing a process-in a computer processor, comprising:

storing a first set of odd nibbles of JH state in a first register;

storing a second set of odd nibbles of JH state in a second register;

storing a first set of even nibbles of JH state in a third register;

storing a second set of even nibbles of JH state in a fourth register;

decoding one or more instructions of a first and a second type;

executing one or more decoded instructions of a first type to perform S-Box mappings on a JH state by

executing the instruction of a first type a first time to perform the S-Box mappings on the first set of odd nibbles and store the results in a first destination register as first odd nibbles results,

executing the instruction of a first type a second time to perform the S-Box mappings on the second set of odd nibbles and store the results in a second destination register as second odd nibbles results,

executing the instruction of a first type a third time to perform the S-Box mappings on the first set of even nibbles and store the results in a third destination register as first even nibbles results, and

executing the instruction of a first type a fourth time to perform the S-Box mappings on the second set of even nibbles and store the results in a fourth destination register as second even nibbles results; and

executing one or more decoded instructions of a second type to perform a linear (L) transformation on the S-Box mappings of the JH state by

performing a first L transformation on the first even nibbles results,

performing a second L transformation on the second even nibbles results,

performing a third L transformation on the first odd nibbles results, and

performing a fourth L transformation on the second odd nibbles results; and

executing one or more decoded instructions of a third type to perform a permutation function by retrieving JH state results from two of the destination registers and performing a permutation function on the JH state results from the two destination registers.

7. The method of claim 6 further comprising performing a swap operation performing the L transformations.

8. The method of claim 6 wherein the swap operation comprises one of swapping adjacent even nibbles, swapping even nibble pairs, swapping even groups of 4 nibbles, swapping even groups of 8 nibbles, swapping even groups of 16 nibbles, swapping even groups of 32 nibbles and swapping even groups of 64 nibbles.