Multi-granular cache management in multi-processor computing environments

• US 9,292,444 B2
• Filed: 09/26/2013
• Issued: 03/22/2016
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Busaba, Fadi Y., Cain, Harold W. III, Gschwind, Michael K., Michael, Maged M., Schwarz, Eric M., Shum, Chung-Lung K., Salapura, Valentina
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US14/037,940
• Publication Number:
  US 20150089159A1
• Time in Patent Office: 908 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry

Abstract

Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode.

Claims

1. A method for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the method comprising:

identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;

identifying an operation in the computing environment, the operation accessing a memory address within a second cache line associated with a second directory entry, the second directory entry associating the second cache line with a second tag and a second set of full-line descriptive bits;

locating the second tag in the side table;

based on the locating, determining that the second cache line is in the sub-line coherency mode; and

based on the determining, accessing and managing only a first sub-cache line portion of the second cache line while performing the operation, the first sub-cache line portion associated with the memory address.

2. The method of claim 1, wherein each member bit in the set of full-line descriptive bits is included in each set of sub-line descriptive bits.

3. The method of claim 2, wherein the set of full-line descriptive bits includes at least one of a valid bit, a transactionally written bit (W), a transactionally read bit (R), and a set of cache protocol supporting bits including at least one of a modified bit (M), an exclusive ownership bit (E), a shared bit (S), and an invalid bit (I).

4. The method of claim 1, wherein the accessing only the first sub-cache line portion of the second cache line comprises:

updating only a first set of sub-line descriptive bits associated with the first sub-cache line portion in the side table.

5. The method of claim 1, wherein the operation is part of a transaction, the method further comprising:

marking only the first sub-cache line portion of the second cache line as transactionally accessed.

6. A computer system for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the computer system comprising:

a memory; and

a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising;

identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;

identifying an operation in the computing environment, the operation accessing a memory address within a second cache line associated with a second directory entry, the second directory entry associating the second cache line with a second tag and a second set of full-line descriptive bits;

locating the second tag in the side table;

based on the locating, determining that the second cache line is in the sub-line coherency mode; and

based on the determining, accessing and managing only a first sub-cache line portion of the second cache line while performing the operation the first sub-cache line portion associated with the memory address.

7. The computer system of claim 6, wherein each member bit in the set of full-line descriptive bits is included in each set of sub-line descriptive bits.

8. The computer system of claim 7, wherein the set of full-line descriptive bits includes at least one of a valid bit, a transactionally written bit (W), a transactionally read bit (R), and a set of cache protocol supporting bits including at least one of a modified bit (M), an exclusive ownership bit (E), a shared bit (S), and an invalid bit (I).

9. The computer system of claim 6, wherein the accessing only the first sub-cache line portion of the second cache line comprises:

updating only a first set of sub-line descriptive bits associated with the first sub-cache line portion in the side table.

10. The computer system of claim 6, wherein the operation is part of a transaction, and wherein the method further comprises:

marking only the first sub-cache line portion of the second cache line as transactionally accessed.

11. The computer system of claim 6, wherein the tag in the side table is further associated with at least one cache line adjacent to the first cache line.

12. The computer system of claim 6, wherein the tag in the side table is saved using a hash value of a memory address associated with the first cache line.

13. A computer program product for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising;

identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;

creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;

identifying an operation in the computing environment, the operation accessing a memory address within a second cache line associated with a second directory entry, the second directory entry associating the second cache line with a second tag and a second set of full-line descriptive bits;

locating the second tag in the side table;

based on the locating, determining that the second cache line is in the sub-line coherency mode; and

based on the determining, accessing and managing only a first sub-cache line portion of the second cache line while performing the operation, the first sub-cache line portion associated with the memory address.

14. The computer program product of claim 13, wherein the accessing only the first sub-cache line portion of the second cache line comprises:

updating only a first set of sub-line descriptive bits associated with the first sub-cache line portion in the side table.

15. The computer program product of claim 13, wherein the method further comprises:

removing the side table entry for the first cache line, wherein the removing places the first cache line the full-line coherency mode.

16. The computer program product of claim 13, wherein the tag in the side table is further associated with at least one cache line adjacent to the first cache line.

17. The computer program product of claim 13, wherein the tag in the side table is saved using a hash value of a memory address associated with the first cache line.