Semiconductor devices and methods providing non-linear compensation of field-effect transistors

• US 9,294,083 B2
• Filed: 05/11/2015
• Issued: 03/22/2016
• Est. Priority Date: 07/07/2012
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Cebi, Haki, Altunkilic, Fikret
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/708,540
• Publication Number:
  US 20150244358A1
• Time in Patent Office: 316 Days
• Field of Search: 327/310, 327/379
• US Class Current: 1/1
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/44 Transmit/receive switching

Abstract

Semiconductor devices and methods are disclosed including switch circuitry providing improved switching performance. A semiconductor die includes a semiconductor substrate, at least one field-effect transistor (FET) formed on the semiconductor substrate, and a compensation circuit connected to a respective source of each of the at least one FET, the compensation circuit configured to compensate a non-linearity effect generated by the at least one FET.

Claims

1. A semiconductor die comprising:

a semiconductor substrate;

at least one field-effect transistor (FET) formed on the semiconductor substrate; and

a compensation circuit connected to a respective source of each of the at least one FET, the compensation circuit configured to compensate a non-linearity effect generated by the at least one FET.

2. The die of claim 1 further comprising an insulator layer disposed between the at least one FET and the semiconductor substrate.

3. The die of claim 2 wherein the die is a silicon-on-insulator (SOI) die.

4. The die of claim 1 wherein the compensation circuit includes a non-linear capacitor.

5. The die of claim 4 wherein the non-linear capacitor includes a metal-oxide-semiconductor (MOS) capacitor.

6. The die of claim 5 wherein the MOS capacitor is configured to generate one or more harmonics to substantially cancel the non-linearity effect generated by the at least one FET.

7. The die of claim 6 wherein the MOS capacitor includes a FET structure.

8. The die of claim 7 wherein the one or more harmonics generated by the MOS capacitor is controlled at least in part by a body bias signal provided to the FET structure of the MOS capacitor.

9. The die of claim 1 further comprising a gate bias circuit connected to and configured to provide a bias signal to a gate of the at least one FET.

10. The die of claim 1 further comprising a body bias circuit connected to and configured to provide a bias signal to a body of the at least one FET.

11. A method for fabricating a semiconductor die, the method comprising:

providing a semiconductor substrate;

forming at least one field-effect transistor (FET) on the semiconductor substrate, each of the at least one FET having a respective source, drain, gate, and body;

forming a compensation circuit on the semiconductor substrate; and

connecting the compensation circuit to the respective source or the respective drain of the at least one FET to thereby allow the compensation circuit to compensate a non-linearity effect generated by the at least one FET.

12. The method of claim 11 further comprising forming an insulator layer between the FET and the semiconductor substrate.

13. The method of claim 11 wherein the compensation circuit includes a non-linear capacitor.

14. The method of claim 13 wherein the non-linear capacitor includes a metal-oxide-semiconductor (MOS) capacitor.

15. The method of claim 14 further comprising generating one or more harmonics to substantially cancel the non-linearity effect generated by the at least one FET using the MOS capacitor.

16. A radio-frequency (RF) switch module comprising:

a packaging substrate configured to receive a plurality of components;

a semiconductor die mounted on the packaging substrate, the die including at least one field-effect transistor (FET); and

a compensation circuit connected to a respective source or a respective drain of each of the at least one FET, the compensation circuit configured to compensate a non-linearity effect generated by the at least one FET.

17. The switch module of claim 16 wherein the semiconductor die is a silicon-on-insulator (SOI) die.

18. The switch module of claim 16 wherein the compensation circuit is part of the semiconductor die.

19. The switch module of claim 16 wherein the compensation circuit is part of a second die mounted on the packaging substrate.

20. The switch module of claim 16 wherein the compensation circuit is disposed at a location outside of the semiconductor die.