Fractional-N PLL-based CDR with a low-frequency reference

• US 9,306,730 B1
• Filed: 02/04/2015
• Issued: 04/05/2016
• Est. Priority Date: 02/04/2015
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Shu, Guanghua, Elzeftawi, Mohamed N., Elkholy, Ahmed M.
• Primary Examiner(s): Ghulamali, Qutbuddin
• Application Number:
  US14/613,652
• Time in Patent Office: 426 Days
• Field of Search: 375/375, 375/374, 375/327, 375/366, 375/376
• US Class Current: 1/1
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

An apparatus relates generally to clock and data recovery. A fractional-N phase-locked loop is for receiving a reference signal, and for providing a proportional signal and an integral signal. A ring oscillator of the fractional-N phase-locked loop is for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal. A data-to-frequency control word converter is for receiving data input and the oscillation signal, and for providing a frequency control word. A fractional-N divider of the fractional-N phase-locked loop is for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop. The phase-frequency detector is for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.

Claims

1. An apparatus for clock and data recovery, comprising:

a fractional-N phase-locked loop for receiving a reference signal, and for providing a proportional signal and an integral signal;

a ring oscillator of the fractional-N phase-locked loop for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal;

a data-to-frequency control word converter for receiving data input and the oscillation signal, and for providing a frequency control word;

a fractional-N divider of the fractional-N phase-locked loop for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop; and

the phase-frequency detector of the fractional-N phase-locked loop for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.

2. The apparatus according to claim 1, wherein the oscillation signal and the ring oscillator are local to a receiver lane for the clock and data recovery for the receiver lane.

3. The apparatus according to claim 1, wherein the reference signal is sourced from a single crystal oscillator.

4. The apparatus according to claim 1, wherein the proportional signal and the integral signal respectively are a proportional current signal and an integral current signal.

5. The apparatus according to claim 1, wherein the fractional-N divider comprises a modulator, a delay line, and a divider coupled for quantization noise cancellation.

6. The apparatus according to claim 1, wherein the data-to-frequency control word converter comprises:

a phase detector for receiving the data input and the oscillation signal, and for providing a phase detection signal;

a first buffer for receiving the phase detection signal, and for scaling the phase detection signal with a proportionality constant to provide a first scaled value;

a second buffer for receiving the phase detection signal, and for scaling the phase detection signal with an integral constant to provide a second scaled value;

an accumulator for accumulating the second scaled value to provide an accumulated value; and

an adder for adding the accumulated value and the first scaled value to provide the frequency control word.

7. The apparatus according to claim 1, further comprising:

a buffer for receiving a phase portion of the frequency control word, and for scaling the phase portion of the frequency control word with a proportionality constant to provide a scaled phase value; and

the ring oscillator for receiving the scaled phase value to control a phase margin of the fractional-N phase-locked loop.

8. The apparatus according to claim 7, wherein the phase margin is controlled to be equal to or greater than 60 degrees.

9. The apparatus according to claim 1, wherein the fractional-N phase-locked loop comprises:

a phase detector for receiving an up signal and a down signal from the phase-frequency detector, and for providing an error signal;

an accumulator for accumulating the error signal to provide an accumulated value;

a first digital-to-analog converter for receiving the accumulated value, and for providing the integral signal;

a second digital-to-analog converter for receiving the up signal and the down signal from the phase-frequency detector, and for providing the proportional signal; and

the fractional-N divider of the fractional-N phase-locked loop for receiving the error signal.

10. The apparatus according to claim 1, wherein no phase interpolator is included for the clock and data recovery.

11. A serial link system for supporting multiple frequencies via multiple lanes, comprising:

a reference oscillator for providing a reference signal;

a plurality of clock and data recovery blocks corresponding to the multiple lanes;

the plurality of clock and data recovery blocks commonly coupled for receiving the reference signal;

wherein each of the plurality of clock and data recovery blocks comprises;

a fractional-N phase-locked loop having a ring oscillator for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal;

a data-to-frequency control word converter for receiving a data input for a corresponding lane of the multiple lanes, for receiving the oscillation signal, and for providing a frequency control word as output; and

a fractional-N divider of the fractional-N phase-locked loop for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop.

12. The serial link system according to claim 11, wherein each of the plurality of clock and data recovery blocks comprises:

the phase-frequency detector of the fractional-N phase locked loop for receiving the reference signal, and for providing a proportional signal and an integral signal;

the ring oscillator of the fractional-N phase-locked loop for receiving the proportional signal and the integral signal, and for providing the oscillation signal; and

the phase-frequency detector of the fractional-N phase-locked loop for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.

13. The serial link system according to claim 12, wherein the data-to-frequency control word converter of each of the plurality of clock and data recovery blocks comprises:

a phase detector for receiving the data input and the oscillation signal, and for providing a phase detection signal;

a first buffer for receiving the phase detection signal, and for scaling the phase detection signal with a proportionality constant to provide a first scaled value;

a second buffer for receiving the phase detection signal, and for scaling the phase detection signal with an integral constant to provide a second scaled value;

an accumulator for accumulating the second scaled value to provide an accumulated value; and

an adder for adding the accumulated value and the first scaled value to provide the frequency control word.

14. The serial link system according to claim 12, wherein each of the plurality of clock and data recovery blocks comprises:

a buffer for receiving a phase portion of the frequency control word, and for scaling the phase portion of the frequency control word with a proportionality constant to provide a scaled phase value; and

the ring oscillator for receiving the scaled phase value, and for controlling a phase margin of the fractional-N phase-locked loop.

15. The serial link system according to claim 12, wherein the fractional-N phase-locked loop of each of the plurality of clock and data recovery blocks comprises:

a phase detector for receiving an up signal and a down signal from the phase-frequency detector, and for providing an error signal;

an accumulator for accumulating the error signal to provide an accumulated value;

a first digital-to-analog converter for receiving the accumulated value, and for providing the integral signal;

a second digital-to-analog converter for receiving the up signal and the down signal from the phase-frequency detector, and for providing the proportional signal; and

the fractional-N divider of the fractional-N phase-locked loop, for receiving the error signal.

16. The serial link system according to claim 12, wherein the plurality of clock and data recovery blocks are respectively of a plurality of receivers, the serial link system further comprising:

a plurality of transmitters corresponding to the plurality of receivers;

wherein each of the plurality of transmitters comprises a transmitter phase-locked loop commonly coupled with the plurality of clock and data recovery blocks, for receiving the reference signal.

17. A method for clock and data recovery, comprising:

receiving a reference signal by a fractional-N phase-locked loop;

generating a proportional signal and an integral signal by the fractional-N phase-locked loop;

receiving the proportional signal and the integral signal by a ring oscillator of the fractional-N phase-locked loop;

outputting an oscillation signal by the ring oscillator at a clock frequency substantially greater than a reference frequency of the reference signal;

receiving a data input and the oscillation signal by a data-to-frequency control word converter;

providing a frequency control word by the data-to-frequency control word converter;

receiving the frequency control word and the oscillation signal by a fractional-N divider of the fractional-N phase-locked loop;

dividing the oscillation signal by the fractional-N divider to output a feedback clock signal;

feeding back the feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop;

receiving the reference signal and the feedback clock signal by the phase-frequency detector of the fractional-N phase-locked loop;

providing an up signal and a down signal from the phase-frequency detector; and

adjusting a phase and frequency of the oscillation signal responsive to the up signal and the down signal.

18. The method according to claim 17, further comprising cancelling quantization noise by the fractional-N divider.

19. The method according to claim 17, further comprising:

receiving a phase portion of the frequency control word by a buffer; and

scaling the phase portion of the frequency control word by the buffer with a proportionality constant to provide a scaled phase value.

20. The method according to claim 19, further comprising inputting the scaled phase value to the ring oscillator, to control a phase margin of the fractional-N phase-locked loop to be equal to or greater than 60 degrees.