Floating point image sensors with tile-based memory

• US 9,307,172 B2
• Filed: 08/13/2014
• Issued: 04/05/2016
• Est. Priority Date: 08/23/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Bock, Nikolai
• Primary Examiner(s): Misleh, Justin P
• Application Number:
  US14/459,068
• Publication Number:
  US 20150055001A1
• Time in Patent Office: 601 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

An image sensor may include an array of image sensor pixels arranged in rows and columns. Each image pixel arranged along a given column may be coupled to analog-to-digital converter (ADC) circuitry that is capable of converting analog pixel signals into a digital floating point equivalent representation. The ADC circuitry may be configured to obtain an illumination value during an auto exposure period. The illumination value, which serves as an exponent value, can be stored as tile data in a tile column memory circuit. During actual readout, the ADC circuitry may be configured to perform mantissa conversion. During mantissa conversion, the ADC circuitry may use a reference voltage value that is adjusted based on the tile data. A mantissa value that is obtained during the mantissa conversion may then be combined with the exponent value for that tile to yield a final floating number point for that image pixel.

Claims

1. An image sensor, comprising:

an array of image sensor pixels arranged in rows and columns, wherein the array has a total number of rows of image sensor pixels, wherein the array is grouped into tiles each of which includes multiple rows and columns of image sensor pixels, and wherein each tile includes a number of rows of image sensor pixels that is less than the total number of rows of image sensor pixels;

a first column output line that is coupled to a first column of image sensor pixels in a given tile;

a second column output line that is coupled to a second column of image sensor pixels in the given tile;

first readout circuitry that is coupled to the first column output line;

second readout circuitry that is coupled to the second column output line; and

a tile column memory circuit that is shared between the first and second readout circuitries,

wherein the first readout circuitry and the second readout circuitry receive pixel signals from the image sensor pixels, wherein the first readout circuitry and the second readout circuitry convert the received pixel signals into floating point numbers, wherein the first readout circuitry and the second readout circuitry generate mantissa information from the received pixel signals, wherein the tile column memory circuit stores exponent information, and wherein the exponent information is combined with the mantissa information to obtain the floating point numbers.

2. The image sensor defined in claim 1, wherein the first readout circuitry includes a first analog-to-digital converter (ADC), and wherein the second readout circuitry includes a second analog-to-digital converter (ADC).

3. The image sensor defined in claim 2, wherein the first readout circuitry further includes a first digital-to-analog converter (DAC), and wherein the second readout circuitry further includes a second digital-to-analog converter (DAC).

4. The image sensor defined in claim 3, wherein the first and second DACs supply reference voltages having a voltage level that is adjusted based on data stored in the tile column memory circuit.

5. The image sensor defined in claim 3, wherein the first DAC comprises an array of binary weighted capacitors, and wherein each capacitor in the array of binary weighted capacitors is selectively switched into use using respective switches.

6. The image sensor defined in claim 5, further comprising:

a control register that receives input signals from the tile column memory circuit and that generates control signals for selectively activating the respective switches.

7. The image sensor defined in claim 6, wherein the control register comprises:

a digital latch having an input and an output;

a first logic gate that is coupled to the input of the digital latch; and

a second logic gate that is coupled to the output of the digital latch.

8. The image sensor defined in claim 7, wherein the digital latch comprises a set-reset latch.

9. The image sensor defined in claim 7, wherein the first and second logic gates comprises logic AND gates.

10. The image sensor defined in claim 1, wherein the first readout circuitry receives analog pixel signals from the array of image sensor pixels and converts the analog pixel signals into floating point numbers.

11. The image sensor defined in claim 1, wherein the array has a total number of columns of image sensor pixels, and wherein each tile includes a number of columns of image sensor pixels that is less than the total number of columns of image sensor pixels.

12. An image sensor, comprising:

an array of image sensor pixels arranged in rows and columns, wherein the array is grouped into tiles each of which includes multiple rows and columns of image sensor pixels;

a first column output line that is coupled to a first column of image sensor pixels in a given tile;

a second column output line that is coupled to a second column of image sensor pixels in the given tile;

first readout circuitry that is coupled to the first column output line and receives first pixel signals from the first column output line, wherein the first readout circuitry generates first mantissa information from the received first pixel signals;

second readout circuitry that is coupled to the second column output line and receives second pixel signals from the second column output line, wherein the second readout circuitry generates second mantissa information from the received second pixel signals; and

a tile column memory circuit that is shared between the first and second readout circuitries, wherein the tile column memory circuit stores exponent information, wherein the exponent information is combined with the first mantissa information to obtain first floating point numbers by the first readout circuitry, and wherein the exponent information is combined with the second mantissa information to obtain second floating point numbers by the second readout circuitry.