Multi-level inverter with flying capacitor topology
First Claim
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1. An apparatus comprising:
- a multi-level inverter comprising a first phase circuit and a second phase circuit, each of the first and the second phase circuits comprising a flying capacitor circuit;
a first set of switches connecting the first phase circuit between voltage input terminals and a second set of switches connecting the second phase circuit between the voltage input terminals; and
an interphase balancing circuit comprising a first pair of terminals connected in parallel across the first phase circuit and a second pair of terminals connected in parallel across the second phase circuit.
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Abstract
A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.
1209 Citations
25 Claims
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1. An apparatus comprising:
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a multi-level inverter comprising a first phase circuit and a second phase circuit, each of the first and the second phase circuits comprising a flying capacitor circuit; a first set of switches connecting the first phase circuit between voltage input terminals and a second set of switches connecting the second phase circuit between the voltage input terminals; and an interphase balancing circuit comprising a first pair of terminals connected in parallel across the first phase circuit and a second pair of terminals connected in parallel across the second phase circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method comprising:
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switching a first phase circuit and a second phase circuit of a multilevel inverter at a first frequency; switching a first pair of switches and a second pair of switches of the multilevel inverter at a second frequency, the first pair of switches connecting the first phase circuit between a pair of voltage input terminals and the second pair of switches connecting the second phase circuit between the pair of voltage input terminals; and removing ripple voltage at the second frequency across the first phase circuit and across the second phase circuit by sharing current between the first phase circuit and second phase circuit. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification