Gate signal adjustment circuit

• US 9,319,036 B2
• Filed: 05/20/2011
• Issued: 04/19/2016
• Est. Priority Date: 05/20/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Chang, Shih Chang, Chang, Ting-Kuo, Jamshidi Roudbari, Abbas, Yu, Cheng-Ho
• Primary Examiner(s): POLO, GUSTAVO D
• Application Number:
  US13/112,862
• Publication Number:
  US 20120293485A1
• Time in Patent Office: 1,796 Days
• Field of Search: 345204-215, 345690-699
• US Class Current: 1/1
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: H03K 5/12 by steepening leading or trailing edges

Abstract

A gate signal adjustment circuit for a display is disclosed. The gate signal adjustment circuit can adjust a transition time of a gate signal used to drive data displaying. The adjustment can be to either speed up or slow down the transition time according to the requirements of the display. In an example, the gate signal adjustment circuit can include multiple transistors, where a first set of the transistors outputs the gate signal and a second set of the transistors outputs an adjustment to the gate signal. The second set of transistors can be the same or different sizes depending on the desirable number of adjustment options. The circuit can also include a control line coupled to the second set of transistors to control the adjustment output. Gate signal adjustment can reduce crosstalk in the display.

Claims

1. A circuit comprising:

a control line from a display driver that transmits an adjustable voltage and is directly connected to a gate of one or more adjustment transistors; and

a timing circuit comprising one or more output transistors and the one or more adjustment transistors coupled together,

the one or more output transistors directly connected to an output signal to transmit the output signal from the timing circuit, and

the one or more adjustment transistors adjusting at least one of a rising time and a falling time of the output signal by receiving the adjustable voltage to couple one or more adjustment signals to the output signal through a source and a drain of the one or more adjustment transistors.

2. The circuit of claim 1, wherein the timing circuit comprises:

a pair of the one or more output transistors coupled together to transmit the output signal.

3. The circuit of claim 2, wherein the timing circuit comprises:

a first adjustment transistor coupled to the pair to transmit an adjustment signal to the pair for adjusting the output signal.

4. The circuit of claim 1, wherein the timing circuit comprises:

a first adjustment transistor coupled to the output signal; and

a second adjustment transistor that receives the adjustable voltage and coupled to the first transistor to transmit an adjustment signal to the first adjustment transistor for adjusting the output signal.

5. The circuit of claim 2, wherein the timing circuit comprises:

an inverter that inverts the adjustable voltage so as to form an inverted adjustable voltage;

a first adjustment transistor coupled to the output signal;

a second adjustment transistor that receives the inverted adjustable voltage and coupled to the pair to transmit a first adjustment signal to the pair for adjusting the output signal; and

a third adjustment transistor that receives the adjustable voltage and coupled to the first adjustment transistor to transmit a second adjustment signal to the first adjustment transistor for adjusting the output signal.

6. The circuit of claim 2, wherein the timing circuit comprises:

an inverter that inverts the adjustable voltage so as to form an inverted adjustable voltage, wherein the one or more adjustment transistors includes a first adjustment transistor, a second adjustment transistor, and a third adjustment transistor,

the first adjustment transistor coupled to the pair to transmit a first adjustment signal to the pair for adjusting the output signal,

the second adjustment transistor receives the inverted adjustable voltage and is coupled to the pair to transmit a second adjustment signal to the pair for adjusting the output signal, and

the third adjustment transistor receives the adjustable voltage and is coupled to the first transistor to transmit a third adjustment signal to the first adjustment transistor for forming the first adjustment signal.

7. The circuit of claim 2, wherein the timing circuit comprises:

a first adjustment transistor coupled to the pair to transmit a first adjustment signal to the pair for adjusting the output signal;

a second adjustment transistor coupled to the pair to transmit a second adjustment signal to the pair for adjusting the output signal; and

a third adjustment transistor that receives the adjustable voltage and is coupled to the first adjustment transistor to transmit a third adjustment signal to the first adjustment transistor for forming the first adjustment signal.

8. The circuit of claim 1, wherein the timing circuit adjusts the falling time.

9. A circuit comprising:

multiple control lines from a display driver that transmit control voltages and are directly connected to a gate of one or more adjustment transistors; and

a timing circuit comprising one or more output transistors and the one or more adjustment transistors coupled together,

the one or more output transistors directly connected to an output signal to transmit the output signal from the timing circuit, and

the one or more adjustment transistors receiving one of the control voltages so as to adjust a transition time of the output signal based on the one control voltage by coupling an adjustment signal to the output signal through a source and a drain of the one or more adjustment transistors, the transition time being at least one of a rising time and a falling time.

10. The circuit of claim 9, wherein the timing circuit comprises:

a pair of the one or more output transistors coupled together to transmit the output signal;

a first adjustment transistor coupled to a first control line to receive a first control voltage and coupled to the pair to transmit a first adjustment signal to the pair for adjusting the transition time of the output signal; and

a second adjustment transistor coupled to a second control line to receive a second control voltage and coupled to the pair to transmit a second adjustment signal to the pair for adjusting the transition time of the output signal.

11. The circuit of claim 9, wherein the timing circuit comprises:

a pair of the one or more output transistors coupled together to transmit the output signal;

a first adjustment transistor coupled to a first control line to receive a first control voltage and coupled to the output signal for adjusting the transition time of the output signal; and

a second adjustment transistor coupled to a second control line to receive a second control voltage and coupled to the output signal for adjusting the transition time of the output signal.

12. The circuit of claim 9, wherein the timing circuit comprises:

a pair of the one or more output transistors coupled together to transmit the output signal

a first adjustment transistor coupled to the output signal for adjusting the transition time of the output signal;

a second adjustment transistor coupled to a first control line to receive a first control voltage and coupled to the first adjustment transistor to transmit a first adjustment signal to the first adjustment transistor for adjusting the transition time of the output signal; and

a third adjustment transistor coupled to a second control line to receive a second control voltage and coupled to the first adjustment transistor to transmit a second adjustment signal to the first adjustment transistor for adjusting the transition time of the output signal.

13. The circuit of claim 9, wherein the timing circuit comprises:

a pair of the one or more output transistors coupled together to transmit the output signal;

a first adjustment transistor coupled to the output signal for adjusting the transition time of the output signal;

a second adjustment transistor coupled to the output signal for adjusting the transition time of the output signal;

a third adjustment transistor coupled to a first control line to receive a first control voltage and coupled to the first adjustment transistor to transmit a first adjustment signal to the first adjustment transistor for adjusting the transition time of the output signal; and

a fourth adjustment transistor coupled to a second control line to receive a second control voltage and coupled to the second adjustment transistor to transmit a second adjustment signal to the second adjustment transistor for adjusting the transition time of the output signal.

14. The circuit of claim 9, wherein the control lines transmit different control voltages.

15. The circuit of claim 9, wherein at least two of the one or more adjustment transistors are different sizes.

16. A display comprising:

a gate signal adjustment circuit that outputs a gate signal by transmitting the gate signal through one or more output transistors, the one or more output transistors directly connected to the gate signal, and adjusts at least one of a rising time and a falling time of the gate signal according to a control voltage by coupling one or more adjustment signals through a source and a drain of the one or more adjustment transistors;

a gate driver that drives the circuit; and

a display driver that sends the control voltage to a gate of the one or more adjustment transistors.

17. The display of claim 16, wherein the circuit comprises multiple components, one set of the components transmits the gate signal and another set of the components transmits an adjustment signal for adjusting the gate signal, the adjusting comprising adjusting the at least one of a rising time and a falling time of the gate signal.

18. The display of claim 16, comprising:

a second gate signal adjustment circuit that adjusts a second gate signal according to a second control voltage, wherein the gate signal adjustment circuit and the second gate signal adjustment circuit are disposed on opposite sides of the display.

19. The display of claim 16 incorporated into at least one of a mobile phone, a media player, or a computer.

20. A gate signal adjustment circuit for a display comprising:

at least one control input from a display driver;

at least one gate signal output; and

multiple transistors that adjust a gate signal and comprised of one or more output transistors and one or more adjustment transistors,

the one or more output transistors directly connected to the at least one gate signal output to transmit the adjusted gate signal, and

the one or more adjustment transistors receiving at least one control signal through the at least one control input directly connected to a gate of the one or more adjustment transistors so as to adjust at least one of a rising time and a falling time of the gate signal by coupling one or more adjustment signals to the gate signal through a source and a drain of the one or more adjustment transistors.

21. The circuit of claim 20, wherein at least some of the transistors form a falling time circuit that adjusts the falling time of the gate signal so as to form an adjusted gate signal.

22. The circuit of claim 20, wherein at least some of the transistors form a rising time circuit that adjusts the rising time of the gate signal so as to form an adjusted gate signal.

23. A method for adjusting a gate signal at a display comprising:

receiving at least one control signal from a display driver at a gate of one or more transistors;

adjusting a transition time of a gate signal according to the received at least one control signal by coupling one or more adjustment signals to the gate signal through a source and a drain of the one or more transistors, the transition time being at least one of a rising time and a falling time; and

outputting the adjusted gate signal through one or more output transistors.

24. The method of claim 23, wherein adjusting the transition time comprises:

actuating at least one transistor of the display to output the gate signal;

actuating at least another transistor of the display with the at least one control signal, the at least another transistor being coupled to the at least one transistor; and

adjusting the transition time of the gate signal with an output of the actuated at least another transistor.

25. The method of claim 23, wherein receiving at least one control signal comprises:

receiving at least one of a digital signal or an analog signal.