Semiconductor device having a bulge portion and manufacturing method therefor

• US 9,320,173 B2
• Filed: 02/18/2013
• Issued: 04/19/2016
• Est. Priority Date: 02/24/2012
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Yamamoto, Kei, Tada, Kazuhiro
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US14/374,363
• Publication Number:
  US 20150016064A1
• Time in Patent Office: 1,156 Days
• Field of Search: 257/666, 257/667, 257/668, 257/691, 257/692, 257/693, 257/696, 257/713, 257/676, 257/707, 257/717, 257/719, 257/720, 361/719, 438/124
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/83951 Forming additional members, e.g. for reinforcing, fillet sealant
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49568 specifically adapted to facilitate heat dissipation
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H05K 7/20409 Outer radiating structures on heat dissipating housings, e.g. fins integrated with the housing

Abstract

A semiconductor device includes a base plate having a first major plane and a second major plane opposite to each other, and having a plurality of fins held upright on the first major plane and a bulge portion formed on the first major plane to encircle the plurality of fins, an insulation layer formed on the second major plane of the base plate, a circuit pattern fixed to the insulation layer, a semiconductor element connected to the circuit pattern, and a sealing resin sealing the insulation layer, the circuit pattern, and the semiconductor element. The bulge portion formed on the first major plane continuously encircles the plurality of fins, the bulge portion has a widthwise margin on an outer peripheral edge of the base plate, and the sealing resin covers an outer peripheral side face of the bulge portion and the widthwise margin.

Claims

1. A semiconductor device comprising:

a base plate having a first major plane and a second major plane opposite to each other, and having a plurality of fins held upright on the first major plane and a bulge portion formed on the first major plane to encircle the plurality of fins;

an insulation layer formed on the second major plane of the base plate;

a circuit pattern fixed to the insulation layer;

a semiconductor element connected to the circuit pattern; and

a sealing resin sealing the insulation layer, the circuit pattern, and the semiconductor element, wherein

the bulge portion formed on the first major plane continuously encircles the plurality of fins,

the base plate has a widthwise margin on an outer peripheral edge of the first major plane of the base plate,

the bulge portion is formed on the widthwise margin and divides the widthwise margin into an outer widthwise margin arranged outside of the bulge portion and an inner widthwise margin arranged inside of the bulge portion, and

the sealing resin covers an outer peripheral side face of the bulge portion and the outer widthwise margin.

2. The semiconductor device of claim 1, wherein the plurality of fins are arranged in a certain direction.

3. The semiconductor device of claim 2, wherein each of the plurality of fins has a slit formed therein to penetrate in the thickness direction of the fins.

4. The semiconductor device of claim 3, wherein the respective slits formed in the plurality of fins are arranged in a line.

5. The semiconductor device of claim 1, wherein the insulation layer contains inorganic powder.

6. The semiconductor device of claim 1, wherein a metal plate is fitted into the base plate.

7. The semiconductor device of claim 1, wherein at least part of the semiconductor elements is constituted with a wide bandgap semiconductor.

8. The semiconductor device of claim 7, wherein the wide bandgap semiconductor is a semiconductor formed of any of silicon carbide, a gallium-nitride-based material, and diamond.

10. The semiconductor device of claim 1, wherein the bulge portion has a narrower width at a position closer to its top.

11. The semiconductor device of claim 1, wherein the widthwise margin has a constant width from the outer peripheral edge of the base plate.

12. The semiconductor device of claim 1, wherein the bulge portion is formed in the middle of the widthwise margin.

13. The semiconductor device of claim 1, wherein the outer widthwise margin and the inner widthwise margin have different widths.

9. A method of manufacturing a semiconductor device, the method comprising:

forming integrally a base plate having a plurality of fins held upright on the base plate and a bulge portion formed on the base plate to encircle continuously the plurality of fins and to have a widthwise margin on an outer peripheral edge of the base plate, the bulge portion being formed on the widthwise margin and dividing the widthwise margin into an outer widthwise margin arranged outside of the bulge portion and an inner widthwise margin arranged inside of the bulge portion;

fixing a semiconductor element to the base plate;

placing the base plate into a molding die provided with a placing stage at a position higher than the bottom of the molding die so that the bulge portion is brought into contact with the placing stage with the plurality of fins down;

injecting a molding resin into the molding die in which the base plate is placed to cover an outer peripheral side face of the bulge portion and the outer widthwise margin; and

curing the injected molding resin by heating.