Method of operating incrementally programmable non-volatile memory

• US 9,324,438 B2
• Filed: 08/05/2014
• Issued: 04/26/2016
• Est. Priority Date: 08/05/2013
• Status: Active Grant

• Current Assignee: Jonker LLC
• Original Assignee: Jonker LLC
• Inventors: Liu, David K. Y.
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/452,275
• Publication Number:
  US 20150036428A1
• Time in Patent Office: 630 Days
• Field of Search: 365/185.03, 365/185.14, 365/185.18
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a V_t representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.

Claims

1. A method of programming a non-volatile device having memory cells each adapted to represent a logic state, and each including a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the method comprising:

setting all the non-volatile device memory cells to a first reference state corresponding to a first logic value represented by a first threshold voltage Vt1;

programming selected ones of the non-volatile device memory cells to a second reference state corresponding to a second logic value represented by a second threshold voltage Vt2, where Vt2>

Vt1;

resetting all the non-volatile device memory cells to a third reference state corresponding to said first logic value and represented by a third threshold voltage Vt3, where Vt3>

=Vt2;

reprogramming selected ones of the non-volatile device memory cells to a fourth reference state corresponding to said second logic value represented by a fourth threshold voltage Vt4, where Vt4>

Vt3;

wherein both programming and erasing a target logic state of the non-volatile device is performed by addition of electrons to the floating gate;

and wherein each cell is reset to a common state prior to programming or reprogramming.

2. The method of claim 1 wherein said resetting operation does not require removal of charge from cells, such that the non-volatile device is operated only as a few times programmable device.

3. The method of claim 1 wherein said cell also stores a third logic value.

4. The method of claim 1 including a step:

time multiplexing a total capacity (Ct) of the non-volatile memory device across P distinct periods such that an available capacity (Ca)=Ct/P at any moment in time.

5. The method of claim 1 wherein the memory cells store a multi-bit logic value during at least one of P distinct programming periods.

6. The method of claim 1 wherein the non-volatile memory device operates as a multi-time programmable array without requiring redundancy for each programming cycle.

7. The method of claim 1 wherein the non-volatile memory device is a multi-level cell that is operated by a controller as a single bit cell with a different program threshold voltage during each programming cycle.

8. The method of claim 7 wherein adjacent program threshold levels of the multi-level cell correspond to logical 0 and 1 states.

9. The method of claim 1 wherein said resetting and reprogramming are performed automatically at predetermined time intervals.

10. The method of claim 1 including a step:

operating a first array in the non-volatile memory device with a first threshold voltage corresponding to a first logical state; and

operating a second array in the non-volatile memory device with a second different threshold voltage corresponding to said same first logical state.

11. The method of claim 1 including a step:

wherein the non-volatile memory device also operates with two different threshold voltages corresponding to a single logical state.

12. A method of programming a CMOS logic process compatible non-volatile device having a memory array with memory cells each adapted to represent a logic state, and each including a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the method comprising:

setting all the non-volatile device memory cells in the memory array to a first reference state corresponding to a first logic value represented by a first threshold voltage Vt1;

programming selected ones of the non-volatile device memory cells in the memory array to a second reference state corresponding to a second logic value represented by a second threshold voltage Vt2 using hot carrier injection, where Vt2>

Vt1;

resetting all the non-volatile device memory cells in the memory array at predetermined intervals to a third reference state corresponding to said first logic value and represented by a third threshold voltage Vt3 using hot carrier injection, where Vt3>

=Vt2;

wherein said resetting is performed as part of an automated security operation and/or degradation refresh operation in the non-volatile memory device;

reprogramming selected ones of the non-volatile device memory cells in the memory array after said predetermined intervals to a fourth reference state corresponding to said second logic value represented by a fourth threshold voltage Vt4 using hot carrier injection, where Vt4>

Vt3;

wherein both programming and erasing a target logic state of the non-volatile device is performed by addition of hot electrons to the floating gate;

and wherein each cell in the memory cell array is set or reset to a common state prior to programming or reprogramming.

13. The method of claim 12 wherein different memory arrays are implemented in the non-volatile memory device with different threshold voltages corresponding to the same data logic state.

14. The method of claim 12 further including a step of dividing a total capacity (Ct) of the non-volatile memory array containing M cells and N distinct program levels into P distinct periods, comprising:

performing a first program operation in a 1st period of the P distinct periods to store logical data in the M cells of the array using at least two (2) or more separate program levels {PVt1, PVt2} of the N distinct program levels;

performing a second program operation in a subsequent 2nd period of the P distinct periods to store logical data in the M cells of the array using at least (2) separate program levels {PVt3, PVt4} of the N distinct program levels, wherein at least one of {PVt3, PVt4} is different from and greater than {PVt1, PVt2}.