Stage circuit and organic light emitting display using the same

• US 9,330,593 B2
• Filed: 02/20/2013
• Issued: 05/03/2016
• Est. Priority Date: 09/20/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Jang, Hwan-Soo
• Primary Examiner(s): Pham, Long D
• Application Number:
  US13/771,385
• Publication Number:
  US 20140078029A1
• Time in Patent Office: 1,168 Days
• Field of Search: 345 98-100
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/22 using controlled light sources
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

A stage circuit includes an outputting unit having a first node and a second node, the output unit configured to supply a voltage of a first power supply or a voltage of a third input terminal to an output terminal in accordance with voltages applied to the first node and the second node, a first driver configured to control the voltage of the second node in accordance with signals of a first input terminal, a second input terminal, and the third input terminal, and a second driver configured to control the voltage of the first node in accordance with the signal of the second input terminal and the voltage of the second node.

Claims

1. A stage circuit having a first input terminal, a second input terminal, a third input terminal, and an output terminal, the stage circuit comprising:

an outputting unit having a first node and a second node, the outputting unit to supply a voltage of a first power supply to the output terminal according to a voltage applied to the first node and a signal of the third input terminal to the output terminal according to a voltage applied to the second node;

a first driver to control the voltage of the second node in accordance with signals of the first input terminal, the second input terminal, and the third input terminal; and

a second driver to control the voltage of the first node in accordance with the signal of the second input terminal and the voltage of the second node, wherein

the signal of the third input terminal directly controls an on/off operation of a transistor, the transistor included in the first driver.

2. The stage circuit as claimed in claim 1,

wherein the first input terminal receives an output signal of a previous stage circuit or a start signal,

wherein the second input terminal receives a first clock signal, and

wherein the third input terminal receives a second clock signal.

3. The stage circuit as claimed in claim 2,

wherein the first clock signal and the second clock signal have the same period and have phases that do not overlap.

4. The stage circuit as claimed in claim 3,

wherein the first clock signal and the second clock signal have a period equal to two horizontal periods 2H and are supplied in different horizontal periods as low signals.

5. The stage circuit as claimed in claim 2, wherein the start signal is supplied to overlap the first clock signal.

6. The stage circuit as claimed in claim 2, wherein the first driver includes:

a first transistor between the first input terminal and the second node, the first transistor having a gate electrode coupled to the second input terminal; and

a second transistor and a third transistor serially positioned between the second node and the first power supply,

wherein a gate electrode of the second transistor is coupled to the third input terminal, and

wherein a gate electrode of the third transistor is coupled to the first node.

7. The stage circuit as claimed in claim 2, wherein the outputting unit includes:

a fourth transistor between the first power supply and the output terminal, the fourth transistor having a gate electrode coupled to the first node;

a fifth transistor between the output terminal and the third input terminal, the fifth transistor having a gate electrode coupled to the second node;

a first capacitor between the second node and the output terminal; and

a second capacitor between the first node and the first power supply.

8. The stage circuit as claimed in claim 2, wherein the second driver includes:

a sixth transistor between the first node and the second input terminal, the sixth transistor having a gate electrode coupled to the second node; and

a seventh transistor between the first node and a second power supply, the second power supply having a lower voltage than the first power supply, the seventh transistor having a gate electrode coupled to the second input terminal.

9. The stage circuit as claimed in claim 2, wherein the second driver includes:

a sixth transistor between the first node and the second input terminal, the sixth transistor having a gate electrode coupled to the second node; and

a seventh transistor between the first node and the second input terminal, the seventh transistor being diode connected.

10. The stage circuit as claimed in claim 9, wherein the seventh transistor is coupled so that a current flows from the first node to the second input terminal.

11. The stage circuit as claimed in claim 1, further comprising a bidirectional driver coupled to the first input terminal, a fifth input terminal, and the first driver.

12. The stage circuit as claimed in claim 11, wherein the bidirectional driver includes:

a tenth transistor positioned between the first input terminal and the first driver, the tenth transistor being turned on when a first control signal is supplied; and

an eleventh transistor positioned between the fifth input terminal and the first driver, the eleventh transistor being turned on when a second control signal is supplied.

13. The stage circuit as claimed in claim 12,

wherein the first input terminal receives an output signal of a previous stage circuit or a start signal, and

wherein the fifth input terminal receives an output signal of a next stage circuit or a start signal.

14. The stage circuit as claimed in claim 1, wherein the transistor controls the voltage of the second node according to the on/off operation thereof.

15. An organic light emitting display, comprising:

pixels positioned in regions partitioned by scan lines and data lines;

a data driver for supplying data signals to the pixels through the data lines; and

a scan driver for supplying scan signals to the pixels through the scan lines, the scan driver including stage circuits coupled to the scan lines, each of the stage circuits generating a corresponding scan signal of the scan signals and having a first input terminal, a second input terminal, a third input terminal, and an output terminal,

wherein each of the stage circuits includes;

an outputting unit having a first node and a second node, the outputting unit to supply a voltage of a first power supply to the output terminal according to a voltage applied to the first node and a signal of the third input terminal to the output terminal according to a voltage applied to the second node,

a first driver to control the voltage of the second node in accordance with signals of the first input terminal, the second input terminal, and the third input terminal, and

a second driver to control the voltage of the first node in accordance with the signal of the second input terminal and the voltage of the second node, wherein

the signal of the third input terminal directly controls an on/off operation of a transistor, the transistor included in the first driver.

16. The organic light emitting display as claimed in claim 15, wherein a clock signal supplied to the third input terminal is used as the scan signal.

17. The organic light emitting display as claimed in claim 15, wherein the first input terminal receives a scan signal of a previous stage circuit or a start signal.

18. The organic light emitting display as claimed in claim 17,

wherein second input terminals of odd stage circuits receive a first clock signal and third input terminals of odd stage circuits receive a second clock signal, and

wherein second input terminals of even stage circuits receive the second clock signal and third input terminals of even stage circuits receive the first clock signal.

19. The organic light emitting display as claimed in claim 18, wherein the first clock signal and the second clock signal have the same period and have phases that do not overlap.

20. The organic light emitting display as claimed in claim 18, wherein the first driver includes:

a first transistor between the first input terminal and the second node, the first transistor having a gate electrode coupled to the second input terminal; and

a second transistor and a third transistor serially positioned between the second node and the first power supply,

wherein a gate electrode of the second transistor is coupled to the third input terminal, and

wherein a gate electrode of the third transistor is coupled to the first node.

21. The organic light emitting display as claimed in claim 18, wherein the outputting unit includes:

a fourth transistor between the first power supply and the output terminal, the fourth transistor having a gate electrode coupled to the first node;

a fifth transistor between the output terminal and the third input terminal, the fifth transistor having a gate electrode coupled to the second node;

a first capacitor between the second node and the output terminal; and

a second capacitor between the first node and the first power supply.

22. The organic light emitting display as claimed in claim 18, wherein the second driver includes:

a sixth transistor between the first node and the second input terminal, the sixth transistor having a gate electrode coupled to the second node; and

a seventh transistor between the first node and a second power supply, the second power supply having a lower voltage than the first power supply, the seventh transistor having a gate electrode coupled to the second input terminal.

23. The organic light emitting display as claimed in claim 18, wherein the second driver includes:

a sixth transistor between the first node and the second input terminal, the sixth transistor having a gate electrode coupled to the second node; and

a seventh transistor between the first node and the second input terminal, the seventh transistor being diode connected.

24. The organic light emitting display as claimed in claim 23, wherein the seventh transistor is coupled so that a current flows from the first node to the second input terminal.

25. The organic light emitting display as claimed in claim 18, wherein the scan signal of the previous stage circuit or the start signal supplied to the first input terminal overlaps the clock signal supplied to the second input terminal.

26. The organic light emitting display as claimed in claim 15, further comprising a bidirectional driver coupled to the first input terminal, a fifth input terminal, and the first driver.

27. The organic light emitting display as claimed in claim 26, wherein the bidirectional driver includes:

a tenth transistor between the first input terminal and the first driver, the tenth transistor being turned on when a first control signal is supplied; and

an eleventh transistor between the fifth input terminal and the first driver, the eleventh transistor being turned on when a second control signal is supplied.

28. The organic light emitting display as claimed in claim 27,

wherein the first input terminal receives an output signal or a start signal of a previous stage circuit, and

wherein the fifth input terminal receives an output signal or a start signal of a next stage circuit.