Semiconductor device and memory protection method

• US 9,336,065 B2
• Filed: 10/08/2014
• Issued: 05/10/2016
• Est. Priority Date: 02/18/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakai, Hiroto, Maeda, Kenichi, Kanai, Tatsunori
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US14/509,091
• Publication Number:
  US 20150058588A1
• Time in Patent Office: 580 Days
• Field of Search: 711/203, 711/202, 711/103, 711/154, 711/163, 711/E12.091, 711/206, 711/E12.065
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

Claims

1. A memory protection method of a semiconductor device, which uses a memory device, the method comprising:

managing information required to execute a first program as a first workset;

creating a first relationship which holds information included in the first workset and an address of that information in the memory device;

executing the first program with reference to the first relationship;

calling a second program outside the first workset;

managing information required to execute the second program as a second workset;

creating a second relationship which holds information included in the second workset and an address of that information in the memory device, the first relationship and the second relationship each having a same basic configuration so that each workset refers to information in the memory by means of addresses used by said processor; and

executing the second program with reference to the second relationship, wherein the first and second worksets including program code, data required for a programmed operation, and a memory space required to store a result of the programmed operation.

2. The method according to claim 1, wherein the first relationship and the second relationship respectively manage authority, of the first workset and the second workset, for accessing information stored in the memory device.

3. The method according to claim 1, wherein the second relationship allows information for the first workset to be also accessed by the second workset.

4. The method according to claim 1, wherein the memory device is managed by a single-address system.

5. The method according to claim 1, wherein the memory device comprises a nonvolatile semiconductor storage device and a volatile semiconductor storage device, and

when data requested from a processor is held in the volatile semiconductor storage device, the requested data is read out from the volatile semiconductor storage device, and when the requested data is not held in the volatile semiconductor storage device, the requested data is read out from the nonvolatile semiconductor storage device.

6. The method according to claim 1, further comprising when information not included in the first workset is requested, updating the first relationship based on authority for accessing of the first workset to allow the first workset to access the information.

7. The method according to claim 1, further comprising

generating, when information, which is not held in the memory device, is requested during execution of the first program, the requested information;

and

updating the first relationship based on authority for accessing of the first workset to allow the first workset to access the generated information.

8. The method according to claim 1, wherein pieces of information required to execute the first program and the second program are managed as files and directories.

9. The method according to claim 1, when the first workset requires execution of the second program, the processor transits control from the first workset to the second workset, and switches the relationship to be used from the first relationship to the second relationship.

10. A semiconductor device comprising:

a processor; and

a memory device which is provided for the processor,

wherein when the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, the worksets including program code, data required for a programmed operation, and a memory space required to store a result of the programmed operation, and

the processor accesses to the memory device with reference to the corresponding relationships for the respective worksets,

wherein the worksets include a first workset comprising a first program and a second workset comprising a second program,

the relationships include a first relationship and a second relationship, which are respectively associated with the first workset and the second workset, the first relationship and the second relationship each having a same basic configuration so that each workset refers to information in the memory by means of addresses used by said processor, and

when the first workset requires execution of the second program, the processor transits control from the first workset to the second workset, and switches the relationship to be used from the first relationship to the second relationship.

11. The device according to claim 10, wherein the relationships respectively manage authority, of the worksets, for accessing information in the memory device.

12. The device according to claim 10, wherein the relationships are updated to allow information for the first workset to be also accessed by the second workset.

13. The device according to claim 10, wherein the memory device is managed by a single-address system.

14. The device according to claim 10, further comprising:

a memory management device to access the memory device in response to a request from the processor;

wherein the processor includes,

a creation unit to create the first relationship and the second relationship,

a first execution unit to execute the first program,

a second execution unit to execute the second program,

a call unit to call the second program from the first workset, and

a control unit to transit the control from the first execution unit to the second execution unit in response to a request from the call unit; and

wherein the memory management device accesses the memory device with reference to the first relationship under the control of the first execution unit, and accesses the memory device with reference to the second relationship under the control of the second execution unit.

15. The device according to claim 14, wherein the memory device comprises a nonvolatile semiconductor storage device and a volatile semiconductor storage device, and

when data requested from the processor is held in the volatile semiconductor storage device, the memory management device reads out the requested data from the volatile semiconductor storage device, and when the requested data is not held in the volatile semiconductor storage device, the memory management device reads out the requested data from the nonvolatile semiconductor storage device.

16. The device according to claim 10, wherein the processor updates, based on authority for accessing one of the worksets, one of the relationships corresponding to the one of the worksets to allow the one of the worksets to access data not included in the one of the worksets.

17. The device according to claim 10, wherein the processor creates new data in response to a request from one of the worksets, and updates one of the relationships corresponding to the one of the worksets to set authority for accessing the data.

18. The device according to claim 10, wherein the processor manages pieces of information required to execute the programs as files and directories.

20. The device according to claim 10, wherein the first workset includes a first memory space,

the second workset includes a second memory space,

the first relationship inhibits the first workset from referring to an address of the second memory space, and

the second relationship inhibits the second workset from referring to address of the first memory space.

19. A semiconductor device comprising:

a memory device; and

a processor which creates relationships between pieces of information and addresses in the memory device, and access to the memory device by referencing the relationships,

wherein the relationships include a first relationship associated with a first workset, and a second relationship associated with a second workset, the first relationship and the second relationship each having a same basic configuration so that each workset refers to information in the memory by means of addresses used by said processor, the first and second worksets including program code, data required for a programmed operation, and a memory space required to store a result of the programmed operation, and

in a case that the processor transits control from the first workset to the second workset, the processor switches the relationship from the first relationship to the second relationship.