Method and system for accelerating cryptographic processing

• US 9,342,712 B2
• Filed: 06/05/2013
• Issued: 05/17/2016
• Est. Priority Date: 06/08/2012
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Zhuang, Gongyuan
• Primary Examiner(s): PYZOCHA, MICHAEL J
• Application Number:
  US13/910,476
• Publication Number:
  US 20130332744A1
• Time in Patent Office: 1,077 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
• CPC Class Codes: H04L 9/3066 involving algebraic varieties, e.g. elliptic or hyper-elliptic curves

Abstract

A method, an apparatus, and a non-transitory computer readable medium for accelerating cryptographic processing are presented. A cryptographic algorithm is parallelized, which includes breaking the cryptographic algorithm into components, parallelizing an entire component if the component is fully parallelizable, parallelizing part of a component if the component is partially parallelizable, and sequentially executing a component if the component is not parallelizable. Processing of the parallelizable component or the partially parallelizable component is distributed to one or more parallelized devices. The parallelized devices include at least one of: a graphics processing unit or a cryptographic processing device, which may include an integrated cryptographic processor or a cryptographic co-processor.

Claims

1. A method for accelerating cryptographic processing of a cryptographic algorithm, comprising:

breaking the cryptographic algorithm into a plurality of cryptographic primitives;

determining for each of the cryptographic primitives if each cryptographic primitive is capable of being executed in parallel;

executing the cryptographic primitive in parallel if the cryptographic primitive is fully capable of being executed in parallel;

executing a part of the cryptographic primitive in parallel that if the cryptographic primitive is partially capable of being executed in parallel;

sequentially executing the cryptographic primitive if the cryptographic primitive is not capable of being executed in parallel; and

distributing processing of the cryptographic primitive fully capable of being executed in parallel or the partially-capable of being executed in parallel cryptographic primitive to one or more devices capable of parallel execution of the cryptographic primitive.

2. The method according to claim 1, wherein the devices capable of parallel execution of the cryptographic primitive include at least one of:

a graphics processing unit or a cryptographic processing device.

3. The method according to claim 2, wherein the cryptographic processing device includes an integrated cryptographic processor or a cryptographic co-processor.

4. The method according to claim 2, wherein the cryptographic processing device includes one or more cryptographic engines, each cryptographic engine being specific to a particular cryptographic algorithm.

5. The method according to claim 1, wherein the cryptographic primitive executed sequentially is executed on a central processing unit core.

6. The method according to claim 1, wherein the determining if a component is capable of being executed in parallel includes determining available hardware.

7. The method according to claim 6, wherein the determining available hardware includes determining the available hardware at runtime.

8. The method according to claim 1, wherein cryptographic primitives that are capable of being executed in parallel include parallelizable message authentication codes (PMAC);

and

wherein cryptographic primitives that are partially capable of being executed in parallel include multiple data extensions (SSE) for hash functions.

9. A system for accelerating cryptographic processing, comprising:

one or more devices capable of parallel execution of cryptographic primitives of a cryptographic algorithm; and

a central processing unit core, configured to;

break the cryptographic algorithm into a plurality of cryptographic primitives;

determine for each of the cryptographic primitives if each cryptographic primitive is capable of being executed in parallel;

execute the cryptographic primitive in parallel if the cryptographic primitive is fully capable of being executed in parallel;

execute part of the cryptographic primitive in parallel if the cryptographic primitive is partially capable of being executed in parallel;

sequentially execute the cryptographic primitive if the cryptographic primitive is not capable of being executed in parallel; and

distribute processing of the cryptographic primitive fully capable of being executed in parallel or the partially-capable of being executed in parallel cryptographic primitive to one or more devices capable of parallel execution of the cryptographic primitive.

10. The system according to claim 9, wherein the devices capable of parallel execution of the cryptographic primitives include at least one of:

a graphics processing unit or a cryptographic processing device.

11. The system according to claim 10, wherein the cryptographic processing device includes an integrated cryptographic processor or a cryptographic co-processor.

12. The system according to claim 10, wherein the cryptographic processing device includes one or more cryptographic engines, each cryptographic engine being specific to a particular cryptographic algorithm.

13. The system according to claim 9, wherein the central processing unit core is further configured to execute the cryptographic primitives that are executed sequentially.

14. The system according to claim 9, wherein the central processing unit and the one or more devices capable of parallel execution are located on a single die.

15. The system according to claim 9, wherein the central processing unit core is further configured to:

determine if the plurality of cryptographic primitives is capable of being executed in parallel depending on available hardware.

16. The system according to claim 15, wherein the central processing unit core is further configured to:

determine the available hardware at runtime.

17. The system according to claim 9, wherein cryptographic primitives that are capable of being executed in parallel include parallelizable message authentication codes (PMAC);

and

wherein cryptographic primitives that are partially capable of being executed in parallel include multiple data extensions (SSE) for hash functions.

18. A non-transitory computer-readable storage medium storing a set of instructions for execution by a general purpose computer to accelerate cryptographic processing of a cryptographic algorithm, the set of instructions comprising:

a breaking code segment for breaking the cryptographic algorithm into a plurality of cryptographic primitives;

a determining code segment for determining for each of the cryptographic primitives if each cryptographic primitive is capable of being executed in parallel;

a first executing code segment for executing the cryptographic primitive in parallel if the cryptographic primitive is fully capable of being executed in parallel;

a second executing code segment for executing a part of the cryptographic primitive in parallel if the cryptographic primitive is partially capable of being executed in parallel;

a sequentially executing code segment for sequentially executing the cryptographic primitive if the cryptographic primitive is not capable of being executed in parallel; and

a distributing code segment for distributing processing of the cryptographic primitive fully capable of being executed in parallel or the partially capable of being executed in parallel component to one or more devices capable of parallel execution of the cryptographic primitive.

19. The non-transitory computer-readable storage medium according to claim 18, wherein the instructions are hardware description language (HDL) instructions used for manufacturing of a physical device.

20. The non-transitory computer-readable storage medium according to claim 18, wherein the determining code segment includes

determining available hardware.

21. The non-transitory computer-readable storage medium according to claim 20, wherein the determining code segment includes:

determining the available hardware at runtime.

22. The non-transitory computer-readable storage medium according to claim 18, wherein cryptographic primitives that are capable of being executed in parallel include parallelizable message authentication codes (PMAC);

and

wherein cryptographic primitives that are partially capable of being executed in parallel include multiple data extensions (SSE) for hash functions.