Array substrate and display device

• US 9,349,755 B2
• Filed: 09/18/2014
• Issued: 05/24/2016
• Est. Priority Date: 05/29/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Nagayama, Kazuyoshi
• Primary Examiner(s): MENZ, DOUGLAS M
• Application Number:
  US14/443,822
• Publication Number:
  US 20160118408A1
• Time in Patent Office: 614 Days
• Field of Search: 257/72
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate

Abstract

Disclosed is an array substrate including gate lines (210), data lines (220) formed on a base substrate and a plurality of pixel units defined by intersecting the gate lines (210) and the data lines (220). Each pixel unit includes a TFT. In an overlapping area between an active layer (230) and a source (240) of the TFT, the active layer (230) includes at least two first tabs (231) beyond a gate (260) of the TFT which are located on both sides of a central line of the active layer (230) parallel to the gate line (210) respectively and the two first tabs (231) have a same width in a direction of gate line (210). The above-mentioned array substrate can guarantee that the gate-source capacitance is substantially identical to a predesigned capacitance even if the active layer experiences misalignment while being manufactured, thereby decreasing the error of the common electrode voltage V_com. Further disclosed is a display device including the above-mentioned array substrate.

Claims

1. An array substrate, comprising gate lines, data lines, and a plurality of pixel units defined by intersecting the gate lines and the data lines, the gate lines, the data lines and the pixel units being formed on a substrate, wherein each pixel unit comprises a thin film transistor (TFT), in an overlapping area between an active layer and a source of the TFT, the active layer comprises at least two first tabs protruding beyond a gate of the TFT, the at least two first tabs are disposed on both sides of a central line of the active layer parallel to the gate line respectively and have a same width in a direction of gate line;

the at least two first tabs are arranged in symmetry;

the farther from a gate driver side of the array substrate is, the width of the first tabs in the direction of gate line has an increasing tendency.

2. The array substrate of claim 1, wherein in an overlapping area between an active layer and a drain of the TFT, the active layer further comprises at least two second tabs protruding beyond a gate of the TFT, the at least two second tabs are disposed on both sides of the central line of the active layer parallel to the gate line respectively and have a same width in the direction of gate line.

3. The array substrate of claim 2, wherein the at least two second tabs are arranged in symmetry.

4. The array substrate of claim 2, wherein the gate driver is disposed outside the array substrate.

5. The array substrate of claim 1, wherein the pixel units are divided into n groups in terms of columns, wherein 1<

n≦

N, N is a total number of columns;

beginning with a first column of pixel units closest to the gate driver of array substrate, the first tab of active layer of TFT in the i+1^th group of pixel units has a width in the direction of gate line greater than that of the first tab of active layer of TFT in the i^th group of pixel units by Δ

W1_i, wherein 1≦

i≦

n−

1;

the first tabs of active layer of TFT in a same group have a same width in the direction of gate line.

6. The array substrate of claim 5, wherein each group of pixel units has a same number of columns.

7. The array substrate of claim 6, wherein the farther from the gate driver side of the array substrate is, the width of the second tab of the active layer of the TFT in the direction of gate line has an decreasing tendency.

8. The array substrate of claim 7, wherein the pixel units are divided into m groups in terms of columns, wherein 1<

m≦

N, N is a total number of columns;

beginning with a first column of pixel units closest to the gate driver of the array substrate, the second tab of active layer of TFT in the j+1^th group of pixel units has a width in the direction of gate line smaller than that of the second tab of active layer of TFT in the j^th group of pixel units in the direction of gate line by Δ

W2_j, where 1≦

j≦

m−

1;

the second tabs of active layer of TFT in a same group of pixel units have a same width in the direction of gate line.

9. The array substrate of claim 8, wherein each group of pixel units has a same number of columns.

10. The array substrate of claim 8, wherein m=n.

11. The array substrate of claim 10, wherein in condition that i=j, Δ

W1_i=Δ

W2_j.

12. The array substrate of claim 1, wherein a material for the active layer is oxide semiconductor.

13. A display device, comprising the array substrate of claim 1.