Semiconductor device with transistor local interconnects

• US 9,355,910 B2
• Filed: 12/13/2011
• Issued: 05/31/2016
• Est. Priority Date: 12/13/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Rashed, Mahbub, Lin, Irene Y., Soss, Steven, Kim, Jeff, Nguyen, Chinh, Tarabbia, Marc, Johnson, Scott, Kengeri, Subramani, Venkatesan, Suresh
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US13/324,740
• Publication Number:
  US 20130146986A1
• Time in Patent Office: 1,631 Days
• Field of Search: 257/E27.028, 257/E27.029, 257/E27.046, 257/E27.059, 257/E27.06, 257/E27.07, 257/E27.081, 257/E27.098, 257/E27.107, 257/E27.108, 257/E23.019, 257/E23.143, 257/E23.155, 257/E23.157, 257/E23.161, 257/E23.163, 257/E23.168, 257/E23.171, 257/700, 257/750, 257/758, 257/762, 257768-770, 257773-776, 257202-211, 257/E21.577, 257/E21.59, 257/E21.591, 257/E21.593, 257/E21.595, 438/280, 438/199, 438/223, 438/224, 438229-233, 438/241, 438/279, 438299-300, 438/587, 438597-599, 438/614, 438/618, 438620-622, 438629-630, 438/637, 438/648, 438/649, 438/652, 438655-657, 438/666
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a first transistor and a second transistor disposed on said substrate;

each of said transistors comprising a source, a drain, and a gate;

a first CB layer electrically connected to said gate of said first transistor;

a second CB layer electrically connected to said gate of said second transistor; and

a CA layer extending longitudinally between a first end and a second end;

wherein

said first CB layer is electrically connected to said first end of said CA layer;

said second CB layer is electrically connected to said second end of said CA layer;

said gate of said first transistor extends longitudinally along a first line and said gate of said second transistor extends longitudinally along a second line, wherein said first and second lines are generally parallel to one another and spaced apart from one another; and

said CA layer extends generally parallel to said lines and generally perpendicular to said first CB layer and said second CB layer; and

wherein said first CB layer extends longitudinally beyond said gate of said first transistor and/or said second CB layer extends longitudinally beyond said gate of said second transistor.

2. A semiconductor device as set forth in claim 1 wherein said CA layer is disposed between said gates.

3. A semiconductor device as set forth in claim 2 wherein said CA layer defines a length extending parallel to said lines greater than a length of said CB layers extending parallel to said lines.

4. A semiconductor device as set forth in claim 3 further comprising a third transistor having a gate extending longitudinally along said first line and a fourth transistor having a gate extending longitudinally along said second line.

5. A semiconductor device as set forth in claim 4 wherein said gates of said first and third transistors are separated by a gap and said gates of said second and fourth transistors are separated by gap.

6. A semiconductor device as set forth in claim 5 wherein said CA layer extends across said gap.

7. A semiconductor device as set forth in claim 1 wherein said CA layer extends less than 110 nanometers above said substrate.