Flattened substrate surface for substrate bonding
First Claim
1. A bonded substrate assembly comprising:
- a device substrate including a first surface, a second surface opposite to the first surface, a plurality of device structures on the first surface, and an interconnect structure for the device structures, the interconnect structure including a first wiring layer and a second wiring layer between the first wiring layer and the first surface of the device substrate, the second wiring layer of the interconnect structure including an interlayer dielectric layer with a top surface, and the first wiring layer including a first conductive feature projecting above the top surface of the interlayer dielectric layer and a second conductive feature projecting above the top surface of the interlayer dielectric layer, the first and second conductive features each having a height measured relative to the top surface of the interlayer dielectric layer of the second wiring layer;
a final handle substrate bonded to the second surface of the device substrate; and
at least one insulator layer on the top surface of the interlayer dielectric layer, the at least one insulator layer having a planar top surface and a thickness greater than the height of the first and second conductive features,wherein the first wiring layer of the interconnect structure is a top wiring layer, and the first conductive feature of the interconnect structure is a bond pad.
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Accused Products
Abstract
Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.
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Citations
20 Claims
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1. A bonded substrate assembly comprising:
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a device substrate including a first surface, a second surface opposite to the first surface, a plurality of device structures on the first surface, and an interconnect structure for the device structures, the interconnect structure including a first wiring layer and a second wiring layer between the first wiring layer and the first surface of the device substrate, the second wiring layer of the interconnect structure including an interlayer dielectric layer with a top surface, and the first wiring layer including a first conductive feature projecting above the top surface of the interlayer dielectric layer and a second conductive feature projecting above the top surface of the interlayer dielectric layer, the first and second conductive features each having a height measured relative to the top surface of the interlayer dielectric layer of the second wiring layer; a final handle substrate bonded to the second surface of the device substrate; and at least one insulator layer on the top surface of the interlayer dielectric layer, the at least one insulator layer having a planar top surface and a thickness greater than the height of the first and second conductive features, wherein the first wiring layer of the interconnect structure is a top wiring layer, and the first conductive feature of the interconnect structure is a bond pad. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A bonded substrate assembly comprising:
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a device substrate including a first surface, a second surface opposite to the first surface, a plurality of device structures on the first surface, and an interconnect structure for the device structures, the interconnect structure including an interlayer dielectric layer with a top surface, a first conductive feature projecting above the top surface, and a second conductive feature projecting above the top surface, the first and second conductive features each having a height measured relative to the top surface of the interlayer dielectric layer; a final handle substrate bonded to the second surface of the device substrate; and at least one insulator layer on the top surface of the interlayer dielectric layer, the at least one insulator layer having a planar top surface and a thickness greater than the height of the first and second conductive features, wherein the device substrate includes a first product chip, a second product chip, and a kerf street between the first product chip and the second product chip, the device structures and the interconnect structure are on the first product chip, and the at least one insulator layer fills the kerf street to provide the planar top surface. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification