Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCS), including in distributed antenna systems
First Claim
1. A system for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), comprising:
- a controller unit, comprising;
a chip select output port, a clock output port, and a plurality of data input ports each configured to receive a serial digital data stream; and
a processor configured to;
communicate a chip select signal on the chip select output port to receive a serial digital data stream on each of the plurality of data input ports simultaneously; and
communicate a clock signal on the clock output port; and
a plurality of ADCs, each ADC among the plurality of ADCs comprising;
a chip select input port electrically coupled to the chip select output port of the controller unit;
a clock input port electrically coupled to the clock output port of the controller unit; and
a data output port electrically coupled to a corresponding data input port among the plurality of data input ports of the controller unit;
the ADC configured to provide a serial digital data stream on the data output port in response to receiving the clock signal on the clock input port, if the chip select signal is present on the chip select input port.
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Abstract
Systems and methods for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), including in distributed antenna systems, are disclosed. In one embodiment, a controller unit samples a plurality of serial digital data streams simultaneously. To allow the controller unit to sample the multiple serial digital data streams simultaneously from a plurality of ADCs, the controller unit is configured to provide a plurality of data input ports. Each of the ADCs is coupled to a common chip select port and clock signal port on the controller unit. The controller unit communicates a chip select signal on the chip select port to activate all of the ADCs simultaneously to cause each of the ADCs to provide its respective digital data stream to the respective data input port of the controller unit simultaneously for sampling. As a result, fewer or lower-cost components may be used to sample multiple ADCs.
882 Citations
24 Claims
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1. A system for simultaneous sampling of serial digital data streams from multiple analog-to-digital converters (ADCs), comprising:
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a controller unit, comprising; a chip select output port, a clock output port, and a plurality of data input ports each configured to receive a serial digital data stream; and a processor configured to; communicate a chip select signal on the chip select output port to receive a serial digital data stream on each of the plurality of data input ports simultaneously; and communicate a clock signal on the clock output port; and a plurality of ADCs, each ADC among the plurality of ADCs comprising; a chip select input port electrically coupled to the chip select output port of the controller unit; a clock input port electrically coupled to the clock output port of the controller unit; and a data output port electrically coupled to a corresponding data input port among the plurality of data input ports of the controller unit; the ADC configured to provide a serial digital data stream on the data output port in response to receiving the clock signal on the clock input port, if the chip select signal is present on the chip select input port. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for simultaneously sampling serial digital data streams from multiple analog-to-digital converters (ADCs), comprising:
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communicating a chip select signal to a plurality of chip select input ports in a corresponding plurality of ADCs to simultaneously activate the plurality of ADCs; communicating a clock signal to a corresponding plurality of clock input ports in the plurality of ADCs; simultaneously receiving a plurality of serial digital data streams from the corresponding plurality of ADCs in a corresponding data input port among a plurality of data input ports; and simultaneously sampling the plurality of serial digital data streams received in the plurality of data input ports from the plurality of ADCs. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A distributed antenna system (DAS), comprising:
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a plurality of communications components, comprising; a central unit configured to receive a downlink communications signal from a communications system and distribute the downlink communications signal over at least one downlink communications medium to a plurality of remote units; each remote unit among the plurality of remote units configured to receive the downlink communications signal from the central unit over the at least one downlink communications medium and distribute the downlink communications signal to a client device; a controller unit, comprising; a chip select output port, a clock output port, and a plurality of data input ports each configured to receive a serial digital data stream; and a processor configured to; communicate a chip select signal on the chip select output port to receive a serial digital data stream on each of the plurality of data input ports simultaneously; and communicate a clock signal on the clock output port; and a plurality of signal detectors associated with at least one of the plurality of communications components, wherein each signal detector among the plurality of signal detectors comprises; an interface to receive at least a portion of an analog communications signal from the DAS; and an analog-to-digital converter (ADC) comprising; a chip select input port electrically coupled to the chip select output port of the controller unit; a clock input port electrically coupled to the clock output port of the controller unit; and a data output port electrically coupled to a corresponding data input port among the plurality of data input ports of the controller unit; the ADC configured to; receive an analog signal from the corresponding signal detector; and convert the analog signal to provide the serial digital data stream on the data output port in response to receiving the clock signal on the clock input port, if the chip select signal is present on the chip select input port. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification