Protecting the footprint of memory transactions from victimization

• US 9,367,348 B2
• Filed: 08/15/2013
• Issued: 06/14/2016
• Est. Priority Date: 08/15/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Ghai, Sanjeev, Guthrie, Guy L., Jackson, Jonathan R., Williams, Derek E.
• Primary Examiner(s): Verbrugge, Kevin
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US13/967,853
• Publication Number:
  US 20150052313A1
• Time in Patent Office: 1,034 Days
• Field of Search: 711/136
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

Claims

1. A processing unit for a data processing system including a shared memory system, the processing unit comprising:

a processor core;

a cache memory coupled to the processor core, wherein the cache memory includes;

a cache array;

a directory of contents of the cache array, wherein entries in the cache array and directory have a set associative organization and are grouped in multiple congruence classes; and

transactional memory tracking logic that tracks a transaction footprint including one or more cache lines in the cache array accessed by one or more transactional memory access requests of a memory transaction undergoing execution by the processor core, said transactional memory transaction logic comprising;

a directory structure comprising entries for tracking the cache lines within the load and store footprints of memory transactions;

each entry comprising;

an address tag field, a congruence class (CC) field, a way number field for specifying the particular way of the identified congruence class that holds directory information for the specific cache line in the transaction footprint, a load valid (LV) field including a bit indicating whether the cache line is part of a load footprint of a memory transaction, and a store valid (SV) field including a bit indicating whether the cache line is part of a store footprint;

one or more comparator devices, each comparator device comparing a congruence class field of a real address of a transactional or non-transactional memory access request received with the congruence class indicated by the congruence class field of a respective associated TM directory entry and generating a comparator match vector output to identify the set of cache lines in one or more transaction footprints that are at risk of being replaced from the congruence class accessed by the memory access request;

a load mask generator for receiving the match vector output and the way number fields and LV fields of TM directory entries, and generating a load mask by decoding value at the way number field(s) of the TM directory entry or any entry that is identified by match vector and has/have any bit set in LV field, the load mask indicating zero or more ways of the congruence class containing cache lines in the load footprint of memory transaction(s); and

a store mask generator for receiving the match vector output and the way number fields and SVfields of TM directory entries, and generating a store mask by decoding value at the way number field(s) of the TM directory entry or any entry that is identified by match vector and has/have any bit set in SV field, the store mask indicating zero or more ways of the congruence class containing cache lines in the load footprint of memory transaction(s);

wherein the cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory, forms based on the load mask or store mask a working set of ways in the congruence class containing one or more cache lines within the transaction footprint and updates a replacement order of the cache lines in the congruence class,

wherein the update to the replacement order promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set.

2. The processing unit of claim 1, wherein the update to the replacement order updates the replacement order of the target cache line to most recently used (MRU).

3. The processing unit of claim 2, wherein the update to the replacement order updates the replacement order of a most recently used cache line in the transaction footprint other than the target cache line to MRU−

1.

4. The processing unit of claim 1, wherein the directory forms the working set in response to a replacement order update message from the transactional memory tracking logic.

5. The processing unit of claim 1, wherein:

the transaction footprint includes a load footprint and a store footprint; and

the cache memory, in performing the update, excludes from promotion one of a set including the load footprint and the store footprint.

6. The processing unit of claim 1, wherein the cache memory, responsive to formation of an empty working set, updates the replacement order of the cache lines in the congruence class in accordance with a default replacement policy.

7. A data processing system, comprising:

a plurality of processing units in accordance with claim 1; and

an interconnect fabric coupling the plurality of processing units.

8. A design structure tangibly embodied in a machine-readable storage medium device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processing unit for a data processing system including a shared memory system, the processing unit including;

a processor core;

a cache memory coupled to the processor core, wherein the cache memory includes;

a cache array;

a directory of contents of the cache array, wherein entries in the cache array and directory have a set associative organization and are grouped in multiple congruence classes; and

transactional memory tracking logic that tracks a transaction footprint including one or more cache lines in the cache array accessed by one or more transactional memory access requests of a memory transaction undergoing execution by the processor core, said transactional memory transaction logic comprising;

a directory structure comprising entries for tracking the cache lines within the load and store footprints of memory transactions;

each entry comprising;

an address tag field, a congruence class (CC) field, a way number field for specifying the particular way of the identified congruence class that holds directory information for the specific cache line in the transaction footprint, a load valid (LV) field including a bit indicating whether the cache line is part of a load footprint of a memory transaction, and a store valid (SV) field including a bit indicating whether the cache line is part of a store footprint;

one or more comparator devices, each comparator device comparing a congruence class field of a real address of a transactional or non-transactional memory access request received with the congruence class indicated by the congruence class field of a respective associated TM directory entry and generating a comparator match vector output to identify the set of cache lines in one or more transaction footprints that are at risk of being replaced from the congruence class accessed by the memory access request;

a load mask generator for receiving the match vector output and the way number fields and LV fields of TM directory entries, and generating a load mask by decoding value at the way number field(s) of the TM directory entry or any entry that is identified by match vector and has/have any bit set in LV field, the load mask indicating zero or more ways of the congruence class containing cache lines in the load footprint of memory transaction(s); and

a store mask generator for receiving the match vector output and the way number fields and SVfields of TM directory entries, and generating a store mask by decoding value at the way number field(s) of the TM directory entry or any entry that is identified by match vector and has/have any bit set in SV field, the store mask indicating zero or more ways of the congruence class containing cache lines in the load footprint of memory transaction(s);

wherein the cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory, forms based on the load mask or store mask a working set of ways in the congruence class containing one or more cache lines within the transaction footprint and updates a replacement order of the cache lines in the congruence class, wherein the update to the replacement order promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set.

9. The design structure of claim 8, wherein the update to the replacement order updates the replacement order of the target cache line to most recently used (MRU).

10. The design structure of claim 9, wherein the update to the replacement order updates the replacement order of a most recently used cache line in the transaction footprint other than the target cache line to MRU−

1.

11. The design structure of claim 8, wherein the directory forms the working set in response to a replacement order update message from the transactional memory tracking logic.

12. The design structure of claim 8, wherein:

the transaction footprint includes a load footprint and a store footprint; and

the cache memory, in performing the update, excludes from promotion one of a set including the load footprint and the store footprint.

13. The design structure of claim 8, wherein the cache memory, responsive to formation of an empty working set, updates the replacement order of the cache lines in the congruence class in accordance with a default replacement policy.

14. A method of data processing in a data processing system having a processor core and a shared memory system including a cache memory, the method comprising:

the cache memory tracking a transaction footprint including one or more cache lines accessed by one or more transactional memory access requests of a memory transaction undergoing execution by the processor core;

in response to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class of the cache memory;

the cache memory forming a working set of ways in the congruence class containing one or more cache lines within the transaction footprint; and

the cache memory updating a replacement order of the cache lines in the congruence class, wherein the updating includes promoting at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced based on membership of the at least one cache line in the working set, wherein to form the working set of ways, the method further comprises;

tracking the cache lines within the load and store footprints of memory transactions as entries in a directory structure, each entry comprising;

an address tag field, a congruence class (CC) field, a way number field for specifying the particular way of the identified congruence class that holds directory information for the specific cache line in the transaction footprint, a load valid (LV) field including a bit indicating whether the cache line is part of a load footprint of a memory transaction, and a store valid (SV) field including a bit indicating whether the cache line is part of a store footprint;

comparing, at each comparator device of one or more comparator devices, a congruence class field of a real address of a transactional or non-transactional memory access request received with the congruence class indicated by the congruence class field of a respective associated TM directory entry and generating a comparator match vector output to identify the set of cache lines in one or more transaction footprints that are at risk of being replaced from the congruence class accessed by the memory access request;

receiving, at a load mask generator, the match vector output and the way number fields and LV fields of TM directory entries, and generating a load mask by decoding value at the way number field(s) of the TM directory entry or any entry that is identified by match vector and has/have any bit set in LV field, the load mask indicating zero or more ways of the congruence class containing cache lines in the load footprint of memory transaction(s); and

receiving, at a store mask generator, the match vector and the way number fields and SVfields of TM directory entries, and generating a store mask by decoding value at the way number field(s) of the TM directory entry or any entry that is identified by match vector and has/have any bit set in SV field, the store mask indicating zero or more ways of the congruence class containing cache lines in the load footprint of memory transaction(s),

wherein said cache memory forms the working set of ways based on the load mask or store mask.

15. The method of claim 14, wherein the updating includes updating the replacement order of the target cache line to most recently used (MRU).

16. The method of claim 15, wherein the updating includes updating the replacement order of a most recently used cache line in the transaction footprint other than the target cache line to MRU−

1.

17. The method of claim 14, wherein the forming includes a directory of the cache memory forming the working set in response to a replacement order update message from transactional memory tracking logic within the cache memory.

18. The method of claim 14, wherein:

the transaction footprint includes a load footprint and a store footprint; and

the updating further comprises excluding from the promoting one of a set including the load footprint and the store footprint.

19. The method of claim 14, wherein in response to formation of an empty working set, updating the replacement order of the cache lines in the congruence class in accordance with a default replacement policy.