Allocating memory usage based on voltage regulator efficiency

• US 9,367,442 B2
• Filed: 07/12/2014
• Issued: 06/14/2016
• Est. Priority Date: 07/12/2014
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: Lenovo Enterprise Solutions (Singapore) Pte., Ltd. (Lenovo Group Ltd.)
• Inventors: DeCesaris, Michael, Parsonese, James J., Remis, Luke D., Totten, Brian C.
• Primary Examiner(s): Rutz, Jared
• Assistant Examiner(s): Doan, Khoa D
• Application Number:
  US14/329,902
• Publication Number:
  US 20160011962A1
• Time in Patent Office: 703 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/3037 where the computing system component is a memory, e.g. virtual memory, cache accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/254 Distributed memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods for allocating memory usage based on voltage regulator efficiency are disclosed. According to an aspect, a method may include receiving a first efficiency value of a first voltage regulator associated with a first memory device among multiple memory devices. The method may also include receiving a second efficiency value of a second voltage regulator associated with a second memory device of the memory devices. The method may also include receiving a request to write data to one of the first memory devices and the second memory device. The method may also include determining whether to write the data to the first memory device or the second memory device based on the first and second efficiency values. Further, the method may include writing the data to the first memory device or the second memory device based on the determination.

Claims

1. A method, comprising:

at a computing device comprising at least one processor and a plurality of memory devices;

receiving a first efficiency value of a first voltage regulator associated with a first memory device of the plurality of memory devices;

receiving a second efficiency value of a second voltage regulator associated with a second memory device of the plurality of memory devices;

receiving a request to write data to one of the first memory device and the second memory device;

comparing the first efficiency value to the second efficiency value;

selecting one of the first memory device or the second memory device based on the comparison; and

writing the data to the selected one of the first memory device or the second memory device.

2. The method of claim 1, wherein receiving the first efficiency value comprises receiving the first efficiency value from the first voltage regulator, and

wherein receiving the second efficiency value comprises receiving the second efficiency value from the second voltage regulator.

3. The method of claim 1, wherein receiving the first efficiency value and the second efficiency value comprises retrieving the first and second efficiency values from a third memory device of the plurality of memory devices.

4. The method of claim 1, wherein the first and second efficiency values each comprise one of a percentage value and a power loss value.

5. The method of claim 1, wherein receiving a request to write data to one of the first memory device and the second memory device comprises receiving a memory access request from an application running on the computing device.

6. The method of claim 1, wherein the comparison indicates which of the first or second voltage regulators is operating most efficiently.

7. The method of claim 6, wherein selecting comprises selecting which of the first voltage regulator and second voltage regulator that is operating most efficiently.

8. The method of claim 1, wherein each of the first memory device and the second memory device comprises a dual inline memory module (DIMM).

9. A system, comprising:

a computing device comprising at least one processor and a plurality of memory devices, the computing device configured to;

receive a first efficiency value of a first voltage regulator associated with a first memory device of the plurality of memory devices;

receive a second efficiency value of a second voltage regulator associated with a second memory device of the plurality of memory devices;

receive a request to write data to one of the first memory device and the second memory device;

compare the first efficiency value to the second efficiency value;

select one of the first memory device or the second memory device based on the comparison; and

write the data to the selected one of the first memory device or the second memory device.