Integrated RF front end with stacked transistor switch

• US 9,369,087 B2
• Filed: 02/10/2014
• Issued: 06/14/2016
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Cable, James S.
• Primary Examiner(s): TRAN, PABLO N
• Application Number:
  US14/177,062
• Publication Number:
  US 20140306767A1
• Time in Patent Office: 855 Days
• Field of Search: 455/333, 455/127.3, 455/341, 455/127.1, 455/127.2, 455/121, 455/126, 455128-129, 455/339, 330/311, 330/277, 330/287, 330/251, 330/136, 330/310, 330/295, 330/124.R, 330/10, 247/341, 247280-281, 247/472
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/0053 with common antenna for more than one band
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/48 : in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04L 27/04 : Modulator circuits; Transmitter circuits

Abstract

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Claims

1. An integrated RF Power Amplifier (PA) circuit, comprising:

a) an input node to accept an input signal with respect to a reference voltage Vref, connected to a first gate G1 of a first MOSFET M1, wherein a source of MOSFET M1 is connected to Vref;

b) a plurality of additional MOSFETs M2 to Mn having associated and corresponding gates G2 to Gn, connected in series with the MOSFET M1 to form a transistor stack, wherein the MOSFET M1 comprises a bottom transistor of the transistor stack, and the MOSFET Mn comprises a top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage Vref and an output drive node, and wherein the output drive node is connected to the drain of the top transistor Mn of the transistor stack;

c) a matching, coupling and filtering circuit connected to the output drive node, wherein the matching, coupling and filtering circuit is disposed between the output drive node and an external antenna; and

d) a corresponding predominantly capacitive element connected directly between each gate, G2 to Gn, and Vref.

2. The integrated RF PA of claim 1, further comprising (e) an output power control input node connected to a power controlling MOSFET that is connected in series connection with M1.

3. The integrated RF PA of claim 2, wherein the power controlling MOSFET is disposed between the reference voltage Vref and a power supply voltage external to the PA.

4. The integrated RF PA of claim 2, wherein the power controlling MOSFET comprises one of the MOSFETs M2 to Mn.

5. The integrated RF PA of claim 1, further comprising an output filter section connected in series with the matching, coupling and filtering circuit and disposed between the matching, coupling and filtering circuit and an RF switch, wherein the RF switch connects the output filter section to the external antenna when the RF switch is in an ON (conducting) state.

6. The integrated RF PA of claim 1, wherein the MOSFETs comprise N-MOSFETs.

7. The integrated RF PA of claim 1, wherein the MOSFETs comprise P-MOSFETs.

8. The integrated RF PA of claim 1, wherein the MOSFETs M1 to Mn are fabricated in a silicon layer of a silicon-on-insulator (SOI) substrate.

9. The integrated RF PA of claim 8, wherein the MOSFETs M1 to Mn have associated and corresponding sources and drains, and wherein the sources and the drains extend through an entire thickness of the silicon layer and further down to an insulating layer of the SOI substrate.

10. The integrated RF PA of claim 1, wherein each MOSFET M1 to Mn of the transistor stack has an associated and corresponding drain-to-source voltage Vds, and wherein the Vds of each MOSFET of the transistor stack are approximately equal.

11. The integrated RF PA of claim 1, wherein each MOSFET M1 to Mn of the transistor stack has an associated and corresponding drain-to-source voltage Vds, and wherein the Vds of each MOSFET of the transistor stack are unequal to each other.

12. The integrated RF PA of claim 1, wherein voltage is divided approximately equally across each MOSFET of the transistor stack.

13. The integrated RF PA of claim 1, wherein voltage is divided unequally across each MOSFET of the transistor stack.

14. The integrated RF PA of claim 1, wherein RF voltage is divided across each transistor of the transistor stack, and wherein an RF voltage across the top transistor Mn is greater than an RF voltage across the bottom transistor M1 but does not exceed a voltage that is 3 times the RF voltage across the bottom transistor M1.

15. The integrated RF PA of claim 1, wherein the PA is implemented as a differential power amplifier.

16. The integrated RF PA of claim 1, wherein the MOSFETs M1 to Mn have associated and corresponding sources and drains, wherein the source of the bottom transistor M1 is connected to Vref, and wherein the MOSFETs M1 to Mn are connected in series by connecting a drain of a preceding transistor in the stack to a source of a next transistor in the transistor stack.

17. The integrated RF PA of claim 1, wherein both RF and DC voltages are divided across the transistor stack, and wherein each MOSFET M2 to Mn has associated and corresponding bias resistors RB2 to RBn connected to their associated and corresponding gates of G2 to Gn, wherein the bias resistors RB2 to RBn are connected to associated and corresponding bias voltages VB2 to VBn, wherein the bias voltages VB2 to VBn may be individually selected to adjust the DC voltage divided across each MOSFET M2 to Mn, and wherein the divided DC voltage across each MOSFET M2 to Mn may be controlled by the bias voltages VB2 to VBn to be identical, or they may be controlled by the bias voltages to be any desired divided DC voltage.

18. An integrated RF Power Amplifier (PA) circuit, comprising:

a) an input node to accept an input signal with respect to a reference voltage Vref, connected to a gate G1 of a first MOSFET M1;

b) a plurality of additional MOSFETs M2 to Mn connected in series with M1 to form a transistor stack, wherein the MOSFET M1 comprises a bottom transistor of the transistor stack, and the MOSFET Mn comprises a top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage Vref and an output drive node, and wherein the output drive node is connected to the drain of the top transistor Mn of the transistor stack; and

(c) a shunt resonant circuit connected between the output drive node and the reference voltage and configured to have a reduced impedance at a frequency that is a harmonic of a center operation frequency F₀ of the PA.

19. The integrated RF PA of claim 18, further comprising (d) a plurality of shunt resonant circuits.

20. The integrated RF PA of claim 18, wherein the plurality of MOSFETs M2 to Mn have associated and corresponding gates (G2 to Gn), and wherein the gates G2 to Gn of all of the MOSFETs M2 to Mn are connected to associated and corresponding gate capacitors, and wherein the gate capacitors are connected to Vref.

21. The integrated RF PA of claim 18, wherein the bottom transistor M1 of the transistor stack has an associated drain and source, and wherein either the source or the drain of M1 is connected to the reference voltage Vref.

22. The integrated RF PA of claim 18, wherein the MOSFETs comprise N-MOSFETs.

23. The integrated RF PA of claim 18, wherein the MOSFETs comprise P-MOSFETs.

24. The integrated RF PA of claim 18, wherein the MOSFETs M1to Mn are fabricated in a silicon layer of a silicon-on-insulator (SOI) substrate.

25. The integrated RF PA of claim 24, wherein the MOSFETs M1 to Mn have associated and corresponding sources and drains, and wherein the sources and the drains extend through an entire thickness of the silicon layer and further down to an insulating layer of the SOI substrate.

26. The integrated RF PA of claim 18, wherein each MOSFET M1 to Mn of the transistor stack has an associated and corresponding drain-to-source voltage Vds, and wherein the Vds of each MOSFET of the transistor stack are approximately equal.

27. The integrated RF PA of claim 18, wherein each MOSFET M1 to Mn of the transistor stack has an associated and corresponding drain-to-source voltage Vds, and wherein the Vds of each MOSFET of the transistor stack are unequal to each other.

28. The integrated RF PA of claim 18, wherein voltage is divided approximately equally across each MOSFET of the transistor stack.

29. The integrated RF PA of claim 18, wherein voltage is divided unequally across each MOSFET of the transistor stack.

30. The integrated RF PA of claim 18, wherein RF voltage is divided across each transistor of the transistor stack, and wherein an RF voltage across the top transistor Mn is greater than the RF voltage across the bottom transistor M1 but does not exceed a voltage that is 3 times the RF voltage across the bottom transistor M1.

31. The integrated RF PA of claim 18, wherein the PA is implemented as a differential RF power amplifier.