Non-volatile memory device with an EPLI comparator

• US 9,378,829 B2
• Filed: 02/07/2013
• Issued: 06/28/2016
• Est. Priority Date: 02/07/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kalderon, Ifat Nitzan, Willis, Max Steven III
• Primary Examiner(s): Elmore, Reba I
• Application Number:
  US13/761,217
• Publication Number:
  US 20140219018A1
• Time in Patent Office: 1,237 Days
• Field of Search: 711/103, 711/156, 711/163, 712/37, 713/340
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 13/225 with priority control
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store EPLI values for programming a number of EPLI bits in one of said plurality of sectors with said stored EPLI values; and a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits.

Claims

1. A non-volatile memory device comprising:

a memory cell array including memory cells distributed among a plurality of sectors;

a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store erase power loss indicator (EPLI) values associated with an erasure operation in a sector of said plurality of sectors, and to program a number of EPLI bits in said sector with said stored EPLI values; and

a comparator to compare said stored EPLI values with EPLI values programmed in said EPLI bits during a last successful erasure operation, and to provide an indication of whether or not said erasure operation in said sector is completed.

2. The non-volatile memory device of claim 1 wherein said controller is further operable to read said EPLI values programmed in said EPLI bits.

3. The non-volatile memory device of claim 1 wherein said controller is further operable to output a signal responsive to the comparison performed by said comparator.

4. The non-volatile memory device of claim 3 wherein said output signal is indicative of said one of said plurality of sectors being a trusted sector.

5. The non-volatile memory device of claim 3 wherein said output signal is indicative of said one of said plurality of sectors being an untrusted sector.

6. The non-volatile memory device of claim 3 including an I/O circuit to communicate said output signal to a device externally connected to the memory device.

7. The non-volatile memory device of claim 1 wherein said comparator is included in said controller.

8. The non-volatile memory device of claim 1 wherein said non-volatile memory cells are multi-level cells.

9. The non-volatile memory device of claim 1 wherein said non-volatile memory cells are two-bit cells.

10. The non-volatile memory device of claim 1 wherein said EPLI values include final EPLI values.

11. The non-volatile memory device of claim 1 wherein said EPLI values include initial EPLI values.

12. The non-volatile memory device of claim 10 wherein said initial EPLI values comprise a same logical value.

13. The non-volatile memory device of claim 1 wherein said EPLI bits are stored in memory locations designated for ECC bits.

14. The non-volatile device of claim 11 wherein said ECC bits are redundant bits.

15. The non-volatile device of claim 1 wherein said number of EPLI bits includes at least two bits.

16. The non-volatile device of claim 1 wherein said number of ELPI bits includes 48 bits.

17. A method of erasing a sector of non-volatile memory cells in a non-volatile memory device comprising:

generating and storing EPLI values associated with an erasure operation in the sector;

programming EPLI bits inside the sector with said EPLI values; and

comparing said stored EPLI values with EPLI values programmed in said EPLI bits during a last successful erasure operation, and providing an indication of whether or not said erasure operation in the sector is completed.

18. The method of claim 17 further comprising programming said EPLI bits with stored final EPLI values.

19. The method of claim 17 further comprising-executing a memory sector erase flow comprising at least the steps of memory cell pre-programming, erasing, and soft programming.

20. The method of claim 17 wherein said stored EPLI values comprise final EPLI values.

21. The method of claim 17 further comprising outputting a signal responsive to said comparison.

22. The method of claim 21 further comprising outputting said signal to a device externally connected to the non-volatile memory device.

23. The method of claim 21 wherein said output signal is indicative of the sector being a trusted sector.

24. The method of claim 23 further comprising performing a blank check on the trusted sector.

25. The method of claim 24 further comprising skipping the trusted sector when a result of said blank check confirms that the sector has been erased.

26. The method of claim 21 wherein said output signal is indicative of said sector being an untrusted sector.

27. The method of claim 19 further comprising executing said memory erase flow on an untrusted sector.

28. The method of claim 19 wherein said memory sector erase flow further includes the step of non-data cell programming.

29. The method of claim 19 wherein said initial EPLI values have a same logical value.

30. The method of claim 19 wherein executing said memory erase flow sets all bits in the sector to a same logical value.