Semiconductor memory device, memory system including the same, and operating method thereof
First Claim
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1. A memory system, comprising:
- a semiconductor memory device including a plurality of memory chips; and
a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips,wherein the controller includes;
a cell current information receiving unit configured to receive cell current information from each of the plurality of memory chips and temporarily store the received cell current information; and
a temperature compensation quantity determining unit configured to generate the temperature compensation data corresponding to each of the plurality of memory chips based on the cell current information stored in the cell current information receiving unit.
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Abstract
Disclosed are a semiconductor memory device, a memory system including the same, and an operating method thereof. The memory system includes: a semiconductor memory device including a plurality of memory chips; and a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips.
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18 Claims
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1. A memory system, comprising:
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a semiconductor memory device including a plurality of memory chips; and a controller configured to measure a cell current of each of the plurality of memory chips, generate temperature compensation data corresponding to the measured cell current, and store the generated temperature compensation data in each of the plurality of memory chips, wherein the controller includes; a cell current information receiving unit configured to receive cell current information from each of the plurality of memory chips and temporarily store the received cell current information; and a temperature compensation quantity determining unit configured to generate the temperature compensation data corresponding to each of the plurality of memory chips based on the cell current information stored in the cell current information receiving unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor memory device, comprising:
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a plurality of memory chips, wherein each of the plurality of memory chips include; a memory cell array including a plurality of memory blocks; a peripheral circuit configured to measure a cell current of a selected memory block among the plurality of memory cell blocks, and store temperature compensation data in one or more of the plurality of memory cell blocks; and a control logic configured to generate the temperature compensation data according to the measured cell current, and control the peripheral circuit to program the generated temperature compensation data in the one or more of the plurality of memory cell blocks, wherein when the measured cell current is decreased, a threshold voltage variation amount of memory cells included in the memory cell array according to a temperature is increased. - View Dependent Claims (10, 11, 12, 13)
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14. A method of a memory system, comprising:
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measuring a cell current for each of a plurality of memory chips; generating temperature compensation data corresponding to each of the plurality of memory chips according to the measured cell current; storing the temperature compensation data in each of the plurality of memory chips; and reading the temperature compensation data stored in each of the plurality of memory chips, setting a read voltage of each of the plurality of memory chips according to the read temperature compensation data, and performing the read operation, wherein the temperature compensation data is generated so that when the cell current is decreased, a compensation quantity of the read voltage is increased. - View Dependent Claims (15, 16, 17, 18)
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Specification