Phase-locked loop (PLL)

• US 9,385,731 B2
• Filed: 07/16/2014
• Issued: 07/05/2016
• Est. Priority Date: 07/16/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Feng Wei, Yen, Kuang-Kai, Chen, Huan-Neng, Hsiung, Lee Tsung, Jou, Chewn-Pu, Staszewski, Robert Bogdan
• Primary Examiner(s): Hernandez, William
• Application Number:
  US14/332,548
• Publication Number:
  US 20160020775A1
• Time in Patent Office: 720 Days
• Field of Search: 327/147, 327/150, 327/156, 327/159
• US Class Current: 1/1
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence

Abstract

A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.

Claims

1. A phase-locked loop (PLL), comprising:

a clock adjuster configured to;

receive an initial clock signal having an initial frequency;

receive a mode control signal; and

responsive to a change in a phase error signal of the PLL being below an error threshold, modify the initial clock signal to a first clock signal based on the mode control signal, the first clock signal having a first frequency; and

a loop filter configured to generate a loop filter output signal based on the first clock signal, the loop filter output signal controlling a bandwidth of the PLL.

2. The PLL of claim 1, the loop filter configured to use the first clock signal to coordinate one or more operations.

3. The PLL of claim 1, the first frequency corresponding to the initial frequency divided by a specified divisor, the specified divisor based on the mode control signal.

4. The PLL of claim 3, the specified divisor corresponding to 2 to the power of a value of the mode control signal.

5. The PLL of claim 1, comprising a phase error circuit configured to:

receive a reference phase signal representing a reference phase;

receive a first output phase signal representing a fractional part of an output phase;

receive a second output phase signal representing an integer part of the output phase; and

output the phase error signal based on at least one of the reference phase signal, the first output phase signal or the second output phase signal.

6. The PLL of claim 5, the phase error circuit comprising a subtractor configured to subtract the fractional part of the output phase and the integer part of the output phase from the reference phase to generate the phase error signal.

7. The PLL of claim 5, comprising a mode controller comprising:

a lock detection circuit configured to;

receive the phase error signal; and

provide a lock signal based on the phase error signal and the error threshold; and

a finite-state machine configured to;

receive the lock signal; and

generate the mode control signal based on the lock signal.

8. The PLL of claim 7, the lock detection circuit comprising:

a flip-flop configured to generate a first signal representing a stored phase error based on the phase error signal during a previous clock cycle;

a subtractor configured to generate a second signal representing a change in a phase error of the phase error signal based on a difference between the stored phase error and the phase error; and

a comparator configured to compare the change in the phase error with the error threshold to generate the lock signal.

9. The PLL of claim 1, the loop filter output signal representing an oscillator tuning word (OTW).

10. The PLL of claim 1, the loop filter configured to adjust the bandwidth to correspond to a specified bandwidth.

11. The PLL of claim 1, the loop filter configured to adjust the bandwidth based on a first bandwidth control signal.

12. The PLL of claim 11, comprising a bandwidth controller configured to generate the first bandwidth control signal based on the mode control signal.

13. The PLL of claim 12, the bandwidth controller configured to:

determine a digitally controlled oscillator (DCO) gain estimate corresponding to a gain of a DCO of the PLL; and

generate a second bandwidth control signal based on the DCO gain estimate.

14. The PLL of claim 13, comprising a gain normalizer configured to:

receive the second bandwidth control signal;

receive the loop filter output signal; and

generate a normalized oscillator tuning word (OTW) signal, representing a normalized OTW, based on the second bandwidth control signal and the loop filter output signal.

15. A method for operating a phase-locked loop (PLL), comprising:

comparing a change in a phase error signal of the PLL to an error threshold;

responsive to determining that the change is below the error threshold, modifying an initial clock signal of the PLL having an initial frequency to a first clock signal having a first frequency to alter power usage of the PLL; and

responsive to the modifying an initial clock signal, modifying a bandwidth of the PLL to a specified bandwidth.

16. The method of claim 15, comprising modifying an oscillator tuning word (OTW) to reduce an impact of the modifying an initial clock signal on the bandwidth.

17. The method of claim 15, comprising modifying an oscillator tuning word (OTW) of the PLL to mitigate an impact of a digitally controlled oscillator (DCO) of the PLL on the bandwidth.

18. A method for operating a phase-locked loop (PLL), comprising:

receiving an initial clock signal having an initial frequency;

receiving a mode control signal;

responsive to a change in a phase error signal of the PLL being below an error threshold, modifying the initial clock signal to generate a first clock signal having a first frequency, the first frequency corresponding to the initial frequency divided by a divisor selected based upon the mode control signal; and

generating a loop filter output signal based on the first clock signal, the loop filter output signal controlling a bandwidth of the PLL.

19. The method of claim 18, the divisor corresponding to 2 to the power of a value of the mode control signal.

20. The method of claim 18, the loop filter output signal representing an oscillator tuning word (OTW).