Accelerated erasure coding system and method
DCFirst Claim
1. A system for accelerated error-correcting code (ECC) processing comprising:
- a processing core for executing computer instructions and accessing data from a main memory, the processing core comprising at least 16 data registers, each of the data registers comprising at least 16 bytes;
one or more non-volatile storage media for storing the computer instructions and the data; and
an input/output (I/O) controller for controlling data transfers between the main memory and the non-volatile storage media,wherein the processing core, the non-volatile storage media, the I/O controller, and the computer instructions are configured to implement an erasure coding system comprising;
a data matrix for holding original data in the main memory;
a check matrix for holding check data in the main memory;
an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and
a thread for executing on the processing core and comprising;
a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor; and
a first sequencer for ordering data accesses through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.
1 Assignment
Litigations
0 Petitions
Accused Products
Abstract
An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.
27 Citations
20 Claims
-
1. A system for accelerated error-correcting code (ECC) processing comprising:
-
a processing core for executing computer instructions and accessing data from a main memory, the processing core comprising at least 16 data registers, each of the data registers comprising at least 16 bytes; one or more non-volatile storage media for storing the computer instructions and the data; and an input/output (I/O) controller for controlling data transfers between the main memory and the non-volatile storage media, wherein the processing core, the non-volatile storage media, the I/O controller, and the computer instructions are configured to implement an erasure coding system comprising; a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core and comprising; a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor; and a first sequencer for ordering data accesses through the data matrix and the encoding matrix using the parallel multiplier to generate the check data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A method of accelerated error-correcting code (ECC) processing on a computing system comprising a processing core for accessing instructions and data from a main memory, one or more non-volatile storage media for storing the instructions and the data, an input/output (I/O) controller for controlling data transfers between the main memory and the non-volatile storage media, and a computer program comprising a plurality of computer instructions for implementing an erasure coding system, the processing core comprising at least 16 data registers, each of the data registers comprising at least 16 bytes, the method comprising:
-
storing the computer program on the non-volatile storage media; executing the computer instructions on the processing core; transferring the data between the main memory and the non-volatile storage media using the I/O controller; arranging original data as a data matrix in the main memory; arranging first factors as an encoding matrix in the main memory, the first factors being for encoding the original data into check data, the check data being arranged as a check matrix in the main memory; and generating the check data using a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor, the generating of the check data comprising ordering data accesses through the data matrix and the encoding matrix using the parallel multiplier. - View Dependent Claims (9, 10, 11, 12, 13, 14)
-
-
15. A non-transitory computer-readable storage medium containing a computer program comprising a plurality of computer instructions for performing accelerated error-correcting code (ECC) processing on a computing system comprising a processing core for accessing instructions and data from a main memory, the processing core comprising at least 16 data registers, each of the data registers comprising at least 16 bytes, the computer instructions being configured to implement an erasure coding system when executed on the computing system by performing the steps of:
-
arranging original data as a data matrix in the main memory; arranging first factors as an encoding matrix in the main memory, the first factors being for encoding the original data into check data, the check data being arranged as a check matrix in the main memory; and generating the check data using a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor, the generating of the check data comprising ordering data accesses through the data matrix and the encoding matrix using the parallel multiplier. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification