Accelerated erasure coding system and method

  • US 9,385,759 B2
  • Filed: 09/11/2015
  • Issued: 07/05/2016
  • Est. Priority Date: 12/30/2011
  • Status: Active Grant
First Claim
Patent Images

1. A system for accelerated error-correcting code (ECC) processing comprising:

  • a processing core for executing computer instructions and accessing data from a main memory, the processing core comprising at least 16 data registers, each of the data registers comprising at least 16 bytes;

    one or more non-volatile storage media for storing the computer instructions and the data; and

    an input/output (I/O) controller for controlling data transfers between the main memory and the non-volatile storage media,wherein the processing core, the non-volatile storage media, the I/O controller, and the computer instructions are configured to implement an erasure coding system comprising;

    a data matrix for holding original data in the main memory;

    a check matrix for holding check data in the main memory;

    an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and

    a thread for executing on the processing core and comprising;

    a parallel multiplier for concurrently multiplying multiple data entries of a matrix by a single factor; and

    a first sequencer for ordering data accesses through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

View all claims
    ×
    ×

    Thank you for your feedback

    ×
    ×