Instruction cache power reduction

  • US 9,396,117 B2
  • Filed: 01/09/2012
  • Issued: 07/19/2016
  • Est. Priority Date: 01/09/2012
  • Status: Active Grant
First Claim
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1. A method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, comprising:

  • looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, where least-recently-used bits for a cacheline set indicate a least-recently-used way in that cacheline set;

    determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline;

    looking up, in the tag array, tags for one or more ways in the designated cacheline set, wherein the looking up tags for one or more ways in the designated cacheline set comprises looking up a tag associated with the most-recently-used way prior to looking up tags in the tag array for other ways in the designated cacheline set;

    looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set; and

    in response to determining a cache hit in the most-recently-used way based on the tag array, activating only the most-recently-used way and outputting the data stored in the most-recently-used way from the data array.

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