Determining categories for memory fail conditions

• US 9,401,222 B1
• Filed: 11/23/2015
• Issued: 07/26/2016
• Est. Priority Date: 11/23/2015
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schlemminger, Nils, Eckert, Martin, Torreiter, Otto A.
• Primary Examiner(s): Nguyen, Steve
• Application Number:
  US14/948,743
• Time in Patent Office: 246 Days
• Field of Search: 714/710, 714/711, 714718-723
• US Class Current: 1/1
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5604 Display of error information
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.

Claims

1. A computer-implemented method comprising:

checking memory cells of a memory cell arrangement with a sequence of test parameter configurations for a malfunction using test parameters from different parameter categories;

storing test parameter configurations for which a malfunction is detected;

assigning each of the stored test parameter configurations with a bit fail count comprising a number of malfunctioning memory cells;

defining an order for the stored test parameter configurations;

creating a relational data structure comprising a plurality of interlinked nodes and a root node such that each test parameter configuration of the test parameter configurations is represented by a path, wherein the test parameters associated with the respective test parameter configurations are assigned to one or more nodes of the plurality of interlinked nodes of the path according to the defined order starting from the root node with the bit fail count detected for the respective test parameter configuration being assigned to the respective path;

combining one or more segments of the relational data structure according to a predefined rule for obtaining one or more test groups;

creating a representation of the bit fail counts of the respective test groups;

applying a filter to the relational data structure including the test groups in order to identify test parameter configurations categories to be further analyzed;

storing, for each test parameter configurations for which a malfunction is detected, a bit fail map comprising information about a spatial distribution pattern of the malfunctioning memory cells; and

determining a spatial distribution pattern of memory cells to be further analyzed using the parameter configuration categories to be further analyzed and the bit fail map.

2. The computer-implemented method of claim 1, further comprising:

responsive to detecting a bit fail, adding respective paths for the associated test parameter configuration.

3. The computer-implemented method of claim 1, wherein creating a relational data structure comprises:

generating, for each stored test parameter configuration, a set of test parameter sub-combinations comprising all sub-combinations of the test parameter configurations of the respective stored test parameter configurations in accordance with a predefined order, wherein each sub-combination of the test parameter configurations of the respective stored test parameter configurations is neglected;

assigning to each test parameter sub-combination the bit fail count of the respective test parameter configuration; and

extending the relational data structure such that each test parameter sub-combination is represented by a path with the test parameters of the respective sub-combination being assigned to the nodes of the path according to the defined order starting from the root node and with the bit fail count of the respective sub-combination assigned to the respective path.

4. The computer-implemented method of claim 1, wherein creating a relational data structure comprises:

for each path to be generated checking whether the relational data structure already comprises a path assigned with an identical starting combination of test parameters;

in case no path assigned with an identical starting combination of test parameters is detected, generating the respective path starting at a root node independently of existing paths; and

assigning the bit fail count of the respective path to each link comprised by the respective path.

5. The computer-implemented method of claim 4, further comprising:

upon detecting one or more paths assigned with an identical starting combination of test parameters, merging the respective path to be generated with one of the detected paths; and

merging the respective path to be generated with the detected path comprising the largest identical starting combination of test parameters.

6. The computer-implemented method of claim 5, further comprising:

checking whether the complete test parameter combination of the detected path comprising the largest identical starting combination of test parameters is identical to the complete test parameter combination of the respective path to be generated; and

upon detecting a respective complete identity, merging the respective path to be generated with the respective detected path by adding the bit fail count of the respective path to be generated to each link of the respective detected path.

7. The computer-implemented method of claim 5, further comprising:

checking whether the complete test parameter combination of the respective path to be generated is identical to the starting test parameter combination of the detected path comprising the largest identical starting combination without being identical to the complete test parameter combination of to the respective detected path; and

upon detecting a respective partial identity, neglecting the respective path to be generated.

8. The computer-implemented method of claim 5, further comprising:

checking whether the detected path comprising the largest identical starting combination of test parameters comprises all test parameters of the respective path to be generated without being identical to the test parameter combination of the respective path to be generated and without the respective starting combination being identical to the test parameter combination of the respective path to be generated; and

upon detecting a respective identity, merging the respective path to be generated with the respective detected path by adding to the detected path at the last node of the respective starting combination a branch comprising nodes assigned with the test parameters not comprised by the respective starting combination such that the path from the root node to the end of the respective branch comprises all test parameters of the respective path to be generated.

9. The computer-implemented method of claim 5, further comprising:

checking whether the detected path comprising the largest identical starting combination of test parameters is not comprising all test parameters of to the respective path to be generated; and

upon detecting that the respective detected path does not comprise all test parameters of the respective path to be generated, merging the respective path to be generated with the respective detected path by adding to the detected path at the last node of the respective starting combination a branch comprising nodes assigned with the test parameters not comprised by the respective starting combination such that the path from the root node to the end of the respective branch comprises all test parameters of the respective path to be generated and adding the bit fail count of the respective path to be generated to each link of the respective branch and the respective starting combination.

10. The computer-implemented method of claim 1, wherein combining one or more segments of the relational data structure according to a predefined rule for obtaining one or more test groups comprises:

selecting segments to be combined by using differences of bit fail counts assigned to the segments as a selection criterion.

11. The computer-implemented method of claim 10, wherein the predefined rule for a first parameter category comprises:

selecting a first set of nodes comprising all nodes of the first hierarchy level of the relational data structure assigned with a first test parameter from the first parameter category;

sorting the first test parameters assigned to the nodes of the first set;

for each pair of adjacent test parameters of the sorted first test parameters determining the difference of the two bit fail counts assigned to the links leading directly to the nodes assigned with the respective adjacent test parameters; and

combining the nodes of the first set into test groups such that the differences calculated for the nodes of each test group are all positive or all negative and within a predefined range.

12. The computer-implemented method of claim 11, further comprising:

for each test group obtained, generating an additional segment by copying all segments starting with a link leading directly to one of the nodes of the first set of nodes and merging the first links and nodes of the copied segments, adding up the bit fail counts assigned to merged links and assigning the merged nodes with a test group ID of the respective test group.

13. The computer-implemented method of claim 12, further comprising:

extending the grouping with respect to a second parameter category;

selecting a second set of nodes comprising all nodes of the next level of hierarchy of the additional segment following the merged nodes which are assigned with a second test parameter from the second parameter category;

sorting the second test parameters assigned to the nodes of the second set;

for each pair of adjacent test parameters of the sorted second test parameters determining the difference of the two bit fail counts assigned to the links leading directly to the nodes assigned with the respective adjacent test parameters; and

combining the nodes of the second set into test groups such that the differences calculated for the nodes of each test group are all positive or all negative and within a predefined range.

14. The computer-implemented method of claim 13, wherein combining the nodes of the second set into test groups such that the differences calculated for the nodes of each test group are all positive or all negative and within a predefined range comprises:

for each test group obtained generating an additional segment by copying the segments starting with a link leading directly to one of the nodes of the second set of nodes and merging the first links and nodes of the copied segments, adding up the bit fail counts assigned to merged links and assigning the merged nodes with a test group ID of the respective test group.

15. The computer-implemented method of claim 11, further comprising:

displaying a representation of all bit fail counts assigned to the links leading directly to the nodes of the first set.

16. The computer-implemented method of claim 15, wherein the representation is a bar diagram wherein a y-axis depicts representing bit fail counts.

17. A computer program product comprising:

one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising;

program instructions to checking memory cells of a memory cell arrangement with a sequence of test parameter configurations for a malfunction using test parameters from different parameter categories;

program instructions to storing test parameter configurations for which a malfunction is detected;

program instructions to assigning each of the stored test parameter configurations with a bit fail count comprising a number of malfunctioning memory cells;

program instructions to define an order for the stored test parameter configurations;

program instructions to create a relational data structure comprising a plurality of interlinked nodes and a root node such that each test parameter configuration of the test parameter configurations is represented by a path, wherein the test parameters associated with the respective test parameter configurations are assigned to one or more nodes of the plurality of interlinked nodes of the path according to the defined order starting from the root node with the bit fail count detected for the respective test parameter configuration being assigned to the respective path;

program instructions to combine one or more segments of the relational data structure according to a predefined rule for obtaining one or more test groups;

program instructions to create a representation of the bit fail counts of the respective test groups;

program instructions to apply a filter to the relational data structure including the test groups in order to identify test parameter configurations categories to be further analyzed;

program instructions to store, for each test parameter configurations for which a malfunction is detected, a bit fail map comprising information about a spatial distribution pattern of the malfunctioning memory cells; and

program instructions to determine a spatial distribution pattern of memory cells to be further analyzed using the parameter configuration categories to be further analyzed and the bit fail map.

18. The computer program product of claim 17, wherein the program instructions stored on the one or more computer readable storage media further comprise:

program instructions to, responsive to detecting a bit fail, add respective paths for the associated test parameter configuration.

19. The computer program product of claim 17, wherein the program instructions to create a relational data structure comprise:

program instructions to generate, for each stored test parameter configuration, a set of test parameter sub-combinations comprising all sub-combinations of the test parameter configurations of the respective stored test parameter configurations in accordance with a predefined order, wherein each sub-combination of the test parameter configurations of the respective stored test parameter configurations is neglected;

program instructions to assign to each test parameter sub-combination the bit fail count of the respective test parameter configuration; and

program instructions to extend the relational data structure such that each test parameter sub-combination is represented by a path with the test parameters of the respective sub-combination being assigned to the nodes of the path according to the defined order starting from the root node and with the bit fail count of the respective sub-combination assigned to the respective path.

20. A computer system comprising:

one or more computer processors;

one or more computer readable storage media; and

program instructions stored on the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising;

program instructions to checking memory cells of a memory cell arrangement with a sequence of test parameter configurations for a malfunction using test parameters from different parameter categories;

program instructions to storing test parameter configurations for which a malfunction is detected;

program instructions to assigning each of the stored test parameter configurations with a bit fail count comprising a number of malfunctioning memory cells;

program instructions to define an order for the stored test parameter configurations;

program instructions to create a relational data structure comprising a plurality of interlinked nodes and a root node such that each test parameter configuration of the test parameter configurations is represented by a path, wherein the test parameters associated with the respective test parameter configurations are assigned to one or more nodes of the plurality of interlinked nodes of the path according to the defined order starting from the root node with the bit fail count detected for the respective test parameter configuration being assigned to the respective path;

program instructions to combine one or more segments of the relational data structure according to a predefined rule for obtaining one or more test groups;

program instructions to create a representation of the bit fail counts of the respective test groups;

program instructions to apply a filter to the relational data structure including the test groups in order to identify test parameter configurations categories to be further analyzed;

program instructions to store, for each test parameter configurations for which a malfunction is detected, a bit fail map comprising information about a spatial distribution pattern of the malfunctioning memory cells; and

program instructions to determine a spatial distribution pattern of memory cells to be further analyzed using the parameter configuration categories to be further analyzed and the bit fail map.