Enhanced physical downlink control channel scrambling and demodulation reference signal sequence generation

• US 9,402,251 B2
• Filed: 08/05/2013
• Issued: 07/26/2016
• Est. Priority Date: 08/03/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Intel Corporation
• Inventors: Han, Seunghee, Zhu, Yuan, Chen, Xiaogang, Qin, Yi, Fwu, Jong-Kae
• Primary Examiner(s): Crutchfield, Christopher
• Assistant Examiner(s): Pham, Tito
• Application Number:
  US14/127,118
• Publication Number:
  US 20140355531A1
• Time in Patent Office: 1,086 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H04J 11/0036 at the receiver
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 27/20 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/2613 Structure of the reference signals
• CPC Class Codes: H04L 27/2692 with preamble design, i.e. with negotiation of the synchronisation sequence with transmitter or sequence linked to the algorithm used at the receiver
• CPC Class Codes: H04L 5/0051 of dedicated pilots, i.e. pilots destined for a single user or terminal
• CPC Class Codes: H04W 72/23 in the downlink direction of a wireless link, i.e. towards a terminal
• CPC Class Codes: H04W 88/08 Access point devices
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Methods, apparatuses, and systems are described to provide enhanced physical downlink control channel scrambling and demodulation reference signal sequence generation.

Claims

1. An apparatus to be employed in an enhance node B (eNB), the apparatus comprising:

scrambling circuitry to receive a bit sequence that includes downlink control information (DCI) to be transmitted on an enhanced physical downlink control channel (EPDCCH) and to scramble the bit sequence based on a cell identifier to provide a scrambled bit sequence; and

modulating circuitry coupled with the scrambling circuitry to receive the scrambled bits and to modulate the scrambled bits, with a quadrature phase shift keying modulation scheme, to provide a block of complex-valued modulation symbols,

wherein the cell identifier is a virtual cell identifier;

the DCI is to be transmitted in a first EPDCCH set;

the virtual cell identifier corresponds to the first EPDDCH set; and

the scrambling circuitry is to scramble the DCI bits based on a scrambling initialization seed c_int given by

c_int=└

n_s/2┘

*2⁹+N_ID^ePDCCH

where n_s is a slot number within a radio frame and N_ID^ePDCCH is the virtual cell identifier.

2. The apparatus of claim 1, wherein the cell identifier is a provided to the scrambling circuitry by a radio resource control layer.

3. The apparatus of claim 2, further comprising:

a reference signal (RS) generator to generate demodulation reference signals associated with the EPDCCH based on the virtual cell identifier.

4. The apparatus of claim 1, further comprising:

cyclic redundancy check (CRC) generating and masking circuitry to generate a bit sequence that includes DCI and CRC bits and to mask the bit sequence based on a radio network temporary identity (RNTI) of a user equipment that is an intended recipient of the DCI.

5. The apparatus of claim 1, wherein the cell identifier is configured by radio resource control (RRC) signaling.

6. The apparatus of claim 1, wherein the apparatus is a mobile device that includes a touchscreen display and one or more cameras.