Memory system and a programming method thereof

• US 9,406,392 B2
• Filed: 06/28/2012
• Issued: 08/02/2016
• Est. Priority Date: 12/19/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kyung, Yoon-Young, Kim, Nam-Ho, Choi, Hyun Jin
• Primary Examiner(s): Rigol, Yaima
• Assistant Examiner(s): Matin, Tasnima
• Application Number:
  US13/535,934
• Publication Number:
  US 20130159607A1
• Time in Patent Office: 1,496 Days
• Field of Search: 711/103, 711/115, 365/185.33, 365/185.29, 365/185.11
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A method of programming a storage device includes determining, at a controller of the storage device, that a first program mode of a plurality of program modes is to be entered in response to first information, wherein the first information includes a parameter associated with temperature, power consumption or input/output workload, and changing, using the controller, a program ratio of a first programming and a second programming of the storage device in the first program mode.

Claims

1. A method of programming a storage device including at least one nonvolatile memory device and a controller configured to control the at least one nonvolatile memory device, comprising:

determining, at the controller, that a first program mode of a plurality of program modes is to be entered in response to first information, wherein the first information includes a parameter associated with temperature, power consumption or input/output workload; and

changing, using the controller, a program ratio of a first programming and a second programming of the at least one nonvolatile memory device in the first program mode,

wherein the at least one nonvolatile memory device includes multi-bit cells,

wherein the first programming is a least significant bit (LSB) program operation on the at least one nonvolatile memory device and the second programming is a most significant bit (MSB) program operation on the at least one nonvolatile memory device,

wherein the program ratio is changed so that the LSB program operation is performed more times than the MSB program operation,

wherein the LSB program operation consumes less power or generates less heat than the MSB program operation.

2. The method of claim 1, wherein the program ratio of the first and second programmings is non-uniform in the first mode.

3. The method of claim 2, wherein the program ratio of the first and second programmings is uniform in a second mode of the plurality of program modes.

4. A method of programming a storage device including at least one nonvolatile memory device and a controller configured to control the at least one nonvolatile memory device, comprising:

determining, at the controller, that a first program mode of a plurality of program modes is to be entered in response to first information, wherein the first information includes a parameter associated with temperature, power consumption or input/output workload; and

changing, using the controller, a program ratio of a first programming, a second programming and a third programming of the at least one nonvolatile memory device in the first program mode,

wherein the at least one nonvolatile memory device includes multi-bit cells,

wherein the first programming is a least significant bit (LSB) program operation on the at least one nonvolatile memory device, the second programming is a center significant bit (CSB) program operation on the at least one nonvolatile memory device and the third programming is a most significant bit (MSB) program operation on the at least one nonvolatile memory device,

wherein the program ratio is changed so that the LSB program operation is performed more times than the MSB program operation,

wherein the LSB program operation consumes less power or generates less heat than the MSB program operation.

5. The method of claim 4, wherein the program ratio is changed such that the LSB program operation is performed more times than each of the CSB and MSB program operations, and wherein the CSB and MSB program operations are performed the same number of times.

6. The method of claim 4, wherein the program ratio is changed such that the LSB and CSB program operations are each performed more times than the MSB program operation, and wherein the LSB and CSB program operations are performed the same number of times.

7. The method of claim 4, wherein the program ratio is changed such that the LSB, CSB and MSB program operations are performed a different number of times from each other.

8. A memory system, comprising:

a plurality of nonvolatile memory devices, wherein each of the nonvolatile memory devices is configured to operate in a first program mode and a second program mode; and

a controller connected to the nonvolatile memory devices via a plurality of channels, wherein the controller is configured to measure a temperature of the memory system and determine, in response to the measured temperature, whether to operate the nonvolatile memory devices in the first program mode or the second program mode,

wherein at least one of the nonvolatile memory devices includes multi-level cells,

wherein the first programming is a least significant bit (LSB) program operation on the at least one of the nonvolatile memory devices and the second programming is a most significant bit (MSB) program operation on the at least one of the nonvolatile memory devices,

wherein the program ratio is changed so that the LSB program operation is performed more times than the MSB program operation,

wherein the LSB program operation consumes less power or less heat than the MSB program operation.

9. The memory system of claim 8, wherein in the first program mode a program ratio of the LSB and MSB program operations is greater than 1:

1 and in the second program mode a program ratio of the LSB and MSB program operations is 1;

1.

10. The memory system of claim 8, wherein each channel includes a plurality of ways, each way including one of the nonvolatile memory devices connected to the channel.

11. The memory system of claim 8, wherein the memory system is included in a solid state drive.