Semiconductor device and method of manufacturing the same

• US 9,406,628 B2
• Filed: 03/13/2014
• Issued: 08/02/2016
• Est. Priority Date: 03/21/2013
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Matsumoto, Masahiro, Maekawa, Kazuyoshi, Fujisawa, Masahiko
• Primary Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US14/210,375
• Publication Number:
  US 20140284790A1
• Time in Patent Office: 873 Days
• Field of Search: 257/737, 438/614
• US Class Current: 1/1
• CPC Class Codes: C22C 21/12 with copper as the next major constituent
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0346 Plating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05582 Two-layer coating
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05664 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/29339 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48664 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48844 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48864 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/78301 : Capillary
• CPC Class Codes: H01L 2224/85045 : using a corona discharge, e.g. electronic flame off [EFO]
• CPC Class Codes: H01L 2224/85203 : Thermocompression bonding
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/85207 : Thermosonic bonding
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/20305 : Ultrasonic frequency [f] 100 Khz=<f< 125 KHz
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device in which reliability of a bonding pad to which a conductive wire is bonded is achieved. A bonding pad having an OPM structure is formed of an Al—Cu alloy film having a Cu concentration of 2 wt % or more. By increasing the Cu concentration, the Al—Cu alloy film forming the bonding pad is hardened. Therefore, the bonding pad is difficult to be deformed by impact in bonding of a Cu wire, and deformation of an OPM film as following the deformation of the bonding pad can be reduced. In this manner, concentration of a stress on the OPM film caused by the impact from the Cu wire can be reduced, and therefore, the breakage of the OPM film can be prevented.

Claims

1. A semiconductor device comprising:

a first insulating film formed on a principal surface of a semiconductor substrate;

an electrode pad formed on the first insulating film and formed of an alloy film to which Cu is added;

a second insulating film formed on the principal surface of the semiconductor substrate so as to cover the electrode pad;

a first opening formed in the second insulating film so as to expose a part of an upper surface of the electrode pad;

a plating film electrically connected to the electrode pad via the first opening;

a plating electrode film formed between a lower surface of the plating film and the exposed part of the upper surface of the electrode pad; and

a plating adhesion film formed on an upper surface of the plating film,

wherein a concentration of the Cu in the alloy film forming the electrode pad is 2 wt % to 10 wt %,

wherein a thickness of the alloy film forming the electrode pad is 0.3 μ

m to 3.0 μ

m, and

wherein a Knoop hardness of the alloy film forming the electrode pad is at least 3 kg/mm².

2. The semiconductor device according to claim 1,

wherein the alloy film forming the electrode pad is an Al—

Cu alloy film.

3. The semiconductor device according to claim 1,

wherein the plating film is formed of a Ni film, a Ti film, a Cr film, or a stacked film formed by stacking any of them, and the plating adhesion film is formed of a Pd film, a Au film, or a stacked film formed by stacking the Pd film and the Au film.

4. The semiconductor device according to claim 1,

wherein the plating electrode film is formed of a Ti film, a Pd film, a Cr film, a Cu film, or a stacked film formed by stacking any of them.

5. The semiconductor device according to claim 1,

wherein a Cu wire is bonded to the plating adhesion film.

6. The semiconductor device according to claim 1, wherein the plating electrode film extends over an entirety of the exposed part of the upper surface of the electrode pad.

7. The semiconductor device according to claim 1, wherein the plating electrode film is also formed over an upper surface portion of the second insulating film.

8. The semiconductor device according to claim 1, wherein the plating electrode film comprises a sputtered film.

9. The semiconductor device according to claim 1, wherein the electrode pad comprises a barrier metal film between the alloy film and the first insulating film, and

the barrier metal film comprises at least one of a Ti film and a TiN film.

10. The semiconductor device according to claim 1, wherein a wire is bonded to an upper surface portion of the plating adhesion film, and

in a cross-sectional view, said upper surface portion is above an upper surface of the plating electrode film and an upper surface portion of the second insulating film that contacts a lower surface of the plating electrode film.

11. A semiconductor device comprising:

a first insulating film formed over a surface of a semiconductor substrate;

an electrode pad formed over the first insulating film, the electrode pad including an alloy film comprising Cu;

a second insulating film formed with a lower surface thereof contacting the first insulating film and at least a first upper surface portion of the electrode pad, the second insulating film having an opening therein that exposes a second upper surface portion of the electrode pad;

a plating electrode film formed with a lower surface thereof contacting the second upper surface portion of the electrode pad;

a plating film formed over the second upper surface portion of the electrode pad with the plating electrode film therebetween, the plating film being electrically connected to the electrode pad through the plating electrode film; and

a plating adhesion film formed with a lower surface thereof contacting an upper surface of the plating film,

wherein a concentration of the Cu in the alloy film is 2 wt % to 10 wt %,

wherein a thickness of the alloy film is 0.3 μ

m to 3.0 μ

m, and

wherein a Knoop hardness of the alloy film is at least 3 kg/mm².

12. The semiconductor device according to claim 11, wherein both the plating electrode film and the plating film are also formed over an upper surface portion of the second insulating film.

13. The semiconductor device according to claim 11, wherein the alloy film is an Al—

Cu alloy film.

14. The semiconductor device according to claim 11, wherein:

the plating film comprises at least one of a Ni film, a Ti film, and a Cr film;

the plating adhesion film comprises at least one of a Pd film and an Au film; and

the plating electrode film comprises at least one of a Ti film, a Pd film, a Cr film, and a Cu film.

15. The semiconductor device according to claim 11, wherein the plating electrode film covers an entirety of the second upper surface portion of the electrode pad exposed by the opening in the second insulating film.

16. The semiconductor device according to claim 11, wherein the electrode pad comprises a barrier metal film between the alloy film and the first insulating film, and

the barrier metal film comprises at least one of a Ti film and a TiN film.

17. The semiconductor device according to claim 11, wherein a wire is bonded to an upper surface portion of the plating adhesion film, and

in a cross-sectional view, said upper surface portion of the plating adhesion film is above an upper surface of the plating electrode film and an upper surface portion of the second insulating film that contacts a lower surface portion of the plating electrode film.