Power supply arrangement for semiconductor device

• US 9,406,648 B2
• Filed: 09/25/2014
• Issued: 08/02/2016
• Est. Priority Date: 09/25/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chuei-Tang, Liu, Monsen, Hsu, Sen-Kuei, Yu, Chen-Hua
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US14/496,327
• Publication Number:
  US 20160093588A1
• Time in Patent Office: 677 Days
• Field of Search: 257/691, 257/713
• US Class Current: 1/1
• CPC Class Codes: B23H 7/10 Supporting, winding or electrical connection of wire-electrode
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 : Memory
• CPC Class Codes: H05K 2201/10515 : Stacked components

Abstract

A semiconductor device includes a device die, a first power supply die, and a second power supply die different from the first power supply die. The device die includes a first circuit and a second circuit. The first power supply die is electrically coupled to the first circuit and configured to supply power for the first circuit. The second power supply die is electrically coupled to the second circuit and configured to supply power for the second circuit. The first and second power supply dies are attached to the device die, and overlap the device die in a thickness direction of the device die.

Claims

1. A semiconductor device, comprising:

a device die comprising a first circuit and a second circuit;

an interposer comprising a first surface, a second surface opposite to the first surface, and a plurality of through vias extending from the first surface to the second surface, the device die being attached to the first surface of the interposer;

a first power supply die attached to the second surface of the interposer, electrically coupled to the first circuit through the interposer, and configured to supply power for the first circuit; and

a second power supply die different from the first power supply die, the second power supply die attached to the second surface of the interposer, electrically coupled to the second circuit through the interposer, and configured to supply power for the second circuit,

wherein the first and second power supply dies overlap the device die in a thickness direction of the device die.

2. The semiconductor device of claim 1, wherein

at least one of the first power supply die or the second power supply die overlaps the corresponding first circuit or second circuit in the thickness direction.

3. The semiconductor device of claim 1, wherein

at least one of the first power supply die or the second power supply die includes a voltage regulator configured to regulate and supply a power supply voltage to the corresponding first circuit or second circuit.

4. The semiconductor device of claim 1, wherein

the first circuit and the second circuit have different first and second power supply voltages, and

the first and second power supply dies include corresponding first and second voltage regulators configured to regulate and supply the corresponding first and second power supply voltages to the corresponding first circuit and second circuit.

5. The semiconductor device of claim 1, wherein

each of the first and second power supply dies has a size, in a plan view of the device die, smaller than a size of the device die.

6. The semiconductor device of claim 1, further comprising:

a power management die different from the first and second power supply dies, the power management die electrically coupled to the first and second power supply dies, and configured to supply at least one of power or a control signal to each of the first and second power supply dies.

7. The semiconductor device of claim 1, wherein

the first circuit and the second circuit are selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an input/output (I/O) module.

8. The semiconductor device of claim 1, wherein

a length of a power connection path from at least one of the first power supply die or the second power supply die to the corresponding first circuit or second circuit is 500 μ

m or less.

9. The semiconductor device of claim 1, wherein

the first and second power supply dies are mounted side-by-side on a surface of the device die.

10. The semiconductor device of claim 1, further comprising:

a plurality of conductive bumps disposed between the device die and the first surface of the interposer, the plurality of conductive bumps bonding the device die to the interposer.

11. The semiconductor device of claim 1, further comprising:

a plurality of first conductive bumps disposed between the second surface of the interposer and the first power supply die, the plurality of first conductive bumps bonding the first power supply die to the interposer;

a plurality of second conductive bumps disposed between the second surface of the interposer and the second power supply die, the plurality of second conductive bumps bonding the second power supply die to the interposer; and

a plurality of third conductive bumps disposed between the first surface of the interposer and the device die, the plurality of third conductive bumps bonding the device die to the interposer,

wherein

the first power supply die is electrically coupled to the first circuit through at least one first conductive bump of the plurality of first conductive bumps, at least one through via of the plurality of through vias, and at least one third conductive bump of the plurality of third conductive bumps, and

the second power supply die is electrically coupled to the second circuit through at least one second conductive bump of the plurality of second conductive bumps, at least one through via of the plurality of through vias, and at least one third conductive bump of the plurality of third conductive bumps.

12. A semiconductor device, comprising:

a device die comprising a first circuit and a second circuit;

a first power supply die electrically coupled to the first circuit and configured to supply power to the first circuit;

a second power supply die electrically coupled to the second circuit and configured to supply power to the second circuit; and

an interposer between the device die and the first power supply die and between the device die and the second power supply die;

wherein, the first power supply die at least partially overlaps the first circuit and the second power supply die at least partially overlaps the second circuit.

13. The semiconductor device of claim 12, wherein

the first power supply die and the second power supply die are completely within an outer periphery of the device die, in a plan view of the device die.

14. The semiconductor device of claim 12, wherein

the first power supply die comprises a voltage regulator configured to provide different voltage levels to the first circuit.

15. The semiconductor device of claim 12, wherein

the first power supply die comprises a voltage regulator configured to turn off the first circuit.

16. The semiconductor device of claim 12, further comprising:

a power management die electrically coupled to the first power supply die and the second power supply die, and configured to supply a common power or a control signal to the first power supply die and the second power supply die.

17. A semiconductor device, comprising:

an interposer comprising a first surface and a second surface;

a device die comprising a first circuit and a second circuit, the first circuit and the second circuit being attached to the first surface of the interposer;

a first power supply die attached to the second surface of the interposer and configured to supply power to the first circuit through the interposer; and

a second power supply die attached to the second surface of the interposer and configured to supply power to the second circuit through the interposer.

18. The semiconductor device of claim 17, wherein

the interposer comprises at least one conductive layer alternating with at least one dielectric layer and is configured to provide electrical connections between the first circuit and the first power supply die and between the second circuit and the second power supply die.

19. The semiconductor device of claim 17, further comprising:

a power management die electrically coupled to the interposer and configured to supply at least one of a common power or a control signal to the first power supply die and the second power supply die through the interposer.

20. The semiconductor device of claim 17, further comprising:

a substrate;

a conductive bump disposed between the substrate and the interposer; and

a power management die attached to the substrate and electrically coupled to the interposer through the conductive bump and configured to supply at least one of a common power or a control signal to the first power supply die and the second power supply die through the interposer.