Array substrate, method for manufacturing the same and display apparatus

• US 9,412,761 B2
• Filed: 07/08/2015
• Issued: 08/09/2016
• Est. Priority Date: 03/31/2012
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Bai, Jinchao, Liu, Yao, Li, Liangliang, Hao, Zhaohui, Sun, Liang
• Primary Examiner(s): McCall Shepard, Sonya D
• Application Number:
  US14/794,240
• Publication Number:
  US 20150311231A1
• Time in Patent Office: 398 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Abstract

An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate (1); a common electrode (2) and a pixel electrode (10) sequentially formed on the substrate (1) and insulated from each other; a thin film transistor comprising a gate electrode (4), an active layer (7), a source electrode (8a) and a drain electrode (8b), wherein the drain electrode (8b) is electrically connected with the pixel electrode (10); a common electrode line (5) disposed in a same layer as the gate electrode (4); and an insulating layer (3) between the gate electrode (4) and the common electrode (2), wherein the common electrode (2) is connected with the common electrode line (5) through a through hole in the insulating layer (3).

Claims

1. An array substrate, comprising:

a substrate;

a common electrode and a pixel electrode sequentially formed on the substrate and insulated from each other;

a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode, wherein the drain electrode is electrically connected with the pixel electrode;

a common electrode line disposed in a same layer as the gate electrode;

wherein the array substrate further comprises an insulating layer between the gate electrode and the common electrode to isolate the gate electrode from the common electrode, and the common electrode is connected with the common electrode line through a first through hole, and

wherein the common electrode is provided on the substrate, the insulating layer covers the common electrode and the substrate, the common electrode line and the gate electrode are provided on the insulating layer, and a portion of the insulating layer covering the common electrode has the first through hole.

2. The array substrate according to claim 1, further comprising a passivation layer covering the source electrode and the drain electrode, wherein

a second through hole penetrates through the passivation layer, and the drain electrode is electrically connected with the pixel electrode through the second through hole.

3. The array substrate according to claim 1, wherein the insulating layer is made of an insulating material with high light transmittance.

4. A display apparatus comprises the array substrate according to claim 1.

6. The array substrate according to claim 1, further comprising a passivation layer covering the source electrode and the drain electrode, wherein

a second through hole penetrates through the passivation layer, and the drain electrode is electrically connected with the pixel electrode through the second through hole.

7. The array substrate according to claim 1, wherein the insulating layer is made of an insulating material with high light transmittance.

5. An array substrate, comprising:

a substrate;

a common electrode and a pixel electrode sequentially formed on the substrate and insulated from each other;

a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode, wherein the drain electrode is electrically connected with the pixel electrode;

a common electrode line disposed in a same layer as the gate electrode;

wherein the array substrate further comprises an insulating layer between the gate electrode and the common electrode to isolate the gate electrode from the common electrode, and the common electrode is connected with the common electrode line through a first through hole,

and wherein

the common electrode is provided on the substrate, the insulating layer covers the common electrode and the substrate, the common electrode line and the gate electrode are provided on the insulating layer, and the common electrode line is provided above the common electrode;

the array substrate further comprises a gate electrode protection layer covering the gate electrode, the common electrode line and the insulating layer;

the active layer is provided on the gate electrode protection layer above the gate electrode;

the source electrode and the drain electrode are provided on the active layer;

the array substrate further comprises a passivation layer covering the source electrode, the drain electrode and the gate electrode protection layer; and

the first through hole is provided above the common electrode and sequentially penetrates through the passivation layer, the gate electrode protection layer, the common electrode line and the insulating layer.